Search Results - Shanan, Hyman

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  1. 1
    A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time

    A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time by Shanan, Hyman, Dalton, Declan, Chillara, Vamshi, Dato, Pablo

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  2. 2
    A 32-42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI

    A 32-42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI by Shehata, Mohamed Atef, Roy, Vivek, Breslin, James, Shanan, Hyman, Keaveney, Michael, Staszewski, Robert Bogdan

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  3. 3
    0.3-4.3 GHz Frequency-Accurate Fractional- N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital \Delta- \Sigma Modulator-Based Divider Controller

    0.3-4.3 GHz Frequency-Accurate Fractional- N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital \Delta- \Sigma Modulator-Based Divider Controller by Kennedy, Michael Peter, Hongjia Mo, Fitzgibbon, Brian, Harney, Austin, Shanan, Hyman, Keaveney, Mike

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  4. 4
    37 dBc Harmonic Rejection in 22-nm FD-SOI

    37 dBc Harmonic Rejection in 22-nm FD-SOI by Mohamed Atef Shehata, Roy, Vivek, Breslin, James, Hyman Shanan, Keaveney, Michael, Robert Bogdan Staszewski

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  5. 5
    37 dBc Harmonic Rejection in 22-nm FD-SOI

    37 dBc Harmonic Rejection in 22-nm FD-SOI by Mohamed Atef Shehata, Roy, Vivek, Breslin, James, Hyman Shanan, Keaveney, Michael, Robert Bogdan Staszewski

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  6. 6
    Correction to "A 32-42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI"

    Correction to "A 32-42-GHz RTWO-Based Frequency Quadrupler Achieving >37 dBc Harmonic Rejection in 22-nm FD-SOI" by Shehata, Mohamed Atef, Roy, Vivek, Breslin, James, Shanan, Hyman, Keaveney, Michael, Staszewski, Robert Bogdan

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  7. 7
    0.3-4.3 GHz Frequency-Accurate Fractional-[Formula Omitted] Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital [Formula Omitted]-[Formula Omitted] Modulator-Based Divider Controller

    0.3-4.3 GHz Frequency-Accurate Fractional-[Formula Omitted] Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital [Formula Omitted]-[Formula Omitted] Modulator-B... by Kennedy, Michael Peter, Mo, Hongjia, Fitzgibbon, Brian, Harney, Austin, Shanan, Hyman, Keaveney, Mike

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  8. 8
    0.3–4.3 GHz Frequency-Accurate Fractional-$N$ Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital $\Delta$-$\Sigma$ Modulator-Based Divider Controller

    0.3–4.3 GHz Frequency-Accurate Fractional-$N$ Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital $\Delta$-$\Sigma$ Modulator-Based Divider Controller by Kennedy, Michael Peter, Mo, Hongjia, Fitzgibbon, Brian, Harney, Austin, Shanan, Hyman, Keaveney, Mike

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  9. 9
    High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators

    High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators by Kennedy, Michael Peter, Fitzgibbon, Brian, Harney, Austin, Shanan, Hyman, Keaveney, Mike

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  10. 10
    A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators

    A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators by Shanan, H.N., Kennedy, M.P.

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  11. 11
    Radio transceivers for wireless personal area networks using IEEE802.15.4

    Radio transceivers for wireless personal area networks using IEEE802.15.4 by Retz, Guido, Quinlan, Philip, Shanan, Hyman, Mulvaney, Kenneth, O'Mahony, Shane, Chanca, Miguel, Crowley, Pat, Billon, Charley, Kalimuddin Khan, Muhammad, Lopez Orive, Jesus Javier

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