Search Results - Shen, Chiuan-Huei

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  1. 1
    Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

    Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs by Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng

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  2. 2
    Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

    Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process by Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng

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  3. 3
    Investigation of Two Bits With Multistate Antifuse on nMOS Poly-Silicon Junctionless GAA OTP

    Investigation of Two Bits With Multistate Antifuse on nMOS Poly-Silicon Junctionless GAA OTP by Chang, Chen-Feng, Shen, Chiuan-Huei, Hsieh, Dong-Ru, Lu, Zong-Han, Lin, Cheng-Chen, Chao, Tien-Sheng

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  4. 4
    Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

    Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit by Chung, Chris Chun-Chih, Shen, Chiuan-Huei, Lin, Jer-Yi, Chin, Chun-Chieh, Chao, Tien-Sheng

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  5. 5
    Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity

    Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity by Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Lee, Sen-Yang, Chao, Tien-Sheng

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  6. 6
    Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations

    Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations by Lin, Jer-Yi, Tsai, Chan-Yi, Shen, Chiuan-Huei, Chung, Chun-Chih, Kumar, Malkundi Puttaveerappa Vijay, Chao, Tien-Sheng

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  7. 7
    Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm × 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process

    Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm × 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-F... by Lee, Shen-Yang, Chen, Han-Wei, Shen, Chiuan-Huei, Kuo, Po-Yi, Chung, Chun-Chih, Huang, Yu-En, Chen, Hsin-Yu, Chao, Tien-Sheng

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