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An efficient VLSI architecture for convolutional code decoding
by
Yeu-Horng Shiau
,
Pei-Yin Chen
,
Hung-Yu Yang
,
Yi-Ming Lin
,
Shi-Gi Huang
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Clock Gating
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Degradation
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Low Power
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Vlsi Architecture
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Ieee Electronic Library (Iel) Conference Proceedings
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