Search Results - Shiau, Yeu-Horng

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  1. 1
    Hardware Implementation of a Fast and Efficient Haze Removal Method

    Hardware Implementation of a Fast and Efficient Haze Removal Method by SHIAU, Yeu-Horng, YANG, Hung-Yu, CHEN, Pei-Yin, CHUANG, Ya-Zhu

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  2. 2
    A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications

    A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications by Shiau, Yeu-Horng, Chen, Pei-Yin, Yang, Hung-Yu, Li, Shang-Yuan

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  3. 3
    VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications

    VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications by Shiau, Yeu-Horng, Kuo, Yao-Tsung, Chen, Pei-Yin, Hsu, Feng-Yuan

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  4. 4
    Retraction Note: FPGA logic design method based on multi resolution image real time acquisition system

    Retraction Note: FPGA logic design method based on multi resolution image real time acquisition system by Li, Cheng-Han, Shiau, Yeu-Horng

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  5. 5
    A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images

    A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images by Chen, Pei-Yin, Huang, Chien-Chuan, Shiau, Yeu-Horng, Chen, Yao-Tung

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  6. 6
    RETRACTED ARTICLE: FPGA logic design method based on multi resolution image real time acquisition system

    RETRACTED ARTICLE: FPGA logic design method based on multi resolution image real time acquisition system by Li, Cheng-Han, Shiau, Yeu-Horng

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  7. 7
    A Low-Cost Hardware Design of Learning-Based One-Dimensional Interpolation for Real-Time Video Applications at the Edge

    A Low-Cost Hardware Design of Learning-Based One-Dimensional Interpolation for Real-Time Video Applications at the Edge by Shiau, Yeu-Horng, Huang, Kuan-Yu, Chen, Pei-Yin, Kuo, Cho-Yu

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  8. 8
    A time division multiplexing algorithm based on FPGA buffer shift to realize high speed image processing

    A time division multiplexing algorithm based on FPGA buffer shift to realize high speed image processing by Li, Cheng-Han, Shiau, Yeu-Horng

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  9. 9
    Design of a dynamic pipelined architecture for fuzzy color correction

    Design of a dynamic pipelined architecture for fuzzy color correction by JOU, Jer-Min, KUANG, Shiann-Rong, SHIAU, Yeu-Horng, CHEN, Ren-Der

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  10. 10
    High Dynamic Range Image Rendering with Order-Statistics Filter

    High Dynamic Range Image Rendering with Order-Statistics Filter by Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang

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  11. 11
    Low Complexity Underwater Image Enhancement Based on Dark Channel Prior

    Low Complexity Underwater Image Enhancement Based on Dark Channel Prior by Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang, Ya-Zhu Zhuang, Yeu-Horng Shiau

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  12. 12
    Efficient Color Image Enhancement Based on Fast and Adaptive Bidimensional Empirical Mode Decomposition

    Efficient Color Image Enhancement Based on Fast and Adaptive Bidimensional Empirical Mode Decomposition by Hung-Yu Yang, Shang-Yuan Li, Pei-Yin Chen, Yeu-Horng Shiau

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  13. 13
    A low-cost Gray prediction search chip for motion estimation

    A low-cost Gray prediction search chip for motion estimation by Jou, Jer Min, Shiau, Yeu-Horng, Chen, Pei-Yin, Kuang, Shiann-Rong

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  14. 14
    Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme

    Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme by Jer Min Jou, Yeu-Horng Shiau, Chin-Chi Liu

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  15. 15
    An efficient VLSI architecture for convolutional code decoding

    An efficient VLSI architecture for convolutional code decoding by Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, Yi-Ming Lin, Shi-Gi Huang

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  16. 16
    An efficient VLSI architecture for HMM-based speech recognition

    An efficient VLSI architecture for HMM-based speech recognition by Jer Min Jou, Yeu-Horng Shiau, Chen-Jen Huang

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  17. 17
    A gray-based block-matching algorithm and its VLSI architecture

    A gray-based block-matching algorithm and its VLSI architecture by Yeu-Horng Shiau, Pei-Yin Chen, Jer Min Jou

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  18. 18
    Dynamic pipeline design of an adaptive binary arithmetic coder

    Dynamic pipeline design of an adaptive binary arithmetic coder by Kuang, Shiann Rong, Jou, Jer Min, Chen, Ren Der, Shiau, Yeu Horng

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  19. 19
    A novel motion estimation algorithm and its VLSI architecture

    A novel motion estimation algorithm and its VLSI architecture by Jer Min Jou, Yeu Horng Shiau, Bu Ren Zheng

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  20. 20
    A grey prediction motion estimator for digital image processing

    A grey prediction motion estimator for digital image processing by Jer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun

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