Search Results - Shridhar Hegde, Shrihari

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    Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit

    Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit by Saligram, Rakshith, Shridhar Hegde, Shrihari, A Kulkarni, Shashidhar, H.R, Bhagyalakshmi, M.K, Venkatesha

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    Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates

    Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates by Saligram, Rakshith, Hegde, Shrihari Shridhar, Kulkarni, Shashidhar A, Bhagyalakshmi, H R, Venkatesha, M K

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    Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit

    Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit by Saligram, Rakshith, Hegde, Shrihari Shridhar, Kulkarni, Shashidhar A, Bhagyalakshmi, H R, Venkatesha, M K

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