Search Results - Sinanoglu, O.

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  1. 1
    Scan Architecture With Align-Encode

    Scan Architecture With Align-Encode by Sinanoglu, O.

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  2. 2
    Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test

    Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test by Almukhaizim, S., Sinanoglu, O.

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  3. 3
    Sneak-path Testing of Memristor-based Memories

    Sneak-path Testing of Memristor-based Memories by Kannan, S., Rajendran, J., Karri, R., Sinanoglu, O.

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  4. 4
    X-Align: Improving the Scan Cell Observability of Response Compactors

    X-Align: Improving the Scan Cell Observability of Response Compactors by Sinanoglu, O., Almukhaizim, S.

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  5. 5
    Security analysis of logic obfuscation

    Security analysis of logic obfuscation by Rajendran, Jeyavijayan, Pino, Youngok, Sinanoglu, Ozgur, Karri, Ramesh

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  6. 6
    Scan Chain Hold-Time Violations: Can They be Tolerated?

    Scan Chain Hold-Time Violations: Can They be Tolerated? by Sinanoglu, O., Schremmer, P.

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  7. 7
    A Novel Mechanism of Anti–T-Lymphocyte Globulin Mediated by Fractalkine in Renal Ischemia–Reperfusion Injury in Rats

    A Novel Mechanism of Anti–T-Lymphocyte Globulin Mediated by Fractalkine in Renal Ischemia–Reperfusion Injury in Rats by Gunay, Y, Inal, A, Yener, N, Sinanoglu, O, Selvi, O, Bircan, H.Y

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  8. 8
    Scan to Nonscan Conversion via Test Cube Analysis

    Scan to Nonscan Conversion via Test Cube Analysis by Sinanoglu, O.

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  9. 9
    Isolation Techniques for Soft Cores

    Isolation Techniques for Soft Cores by Sinanoglu, O., Petrov, T.

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  10. 10
    Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories

    Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories by Kannan, S., Rajendran, J., Karri, R., Sinanoglu, O.

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  11. 11
    Peak Power Reduction Through Dynamic Partitioning of Scan Chains

    Peak Power Reduction Through Dynamic Partitioning of Scan Chains by Almukhaizim, S., Sinanoglu, O.

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  12. 12
    Test power reductions through computationally efficient, decoupled scan chain modifications

    Test power reductions through computationally efficient, decoupled scan chain modifications by Sinanoglu, O., Orailoglu, A.

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  13. 13
    Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits

    Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits by Sinanoglu, Ozgur

    Published in Computer journal
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  14. 14
    Logic encryption: A fault analysis perspective

    Logic encryption: A fault analysis perspective by Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.

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  15. 15
    Testing Chips With Spare Identical Cores

    Testing Chips With Spare Identical Cores by Ramdas, A., Sinanoglu, O.

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  16. 16
    Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs

    Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs by Valente, L., Veeran, A., Sinigaglia, M., Tortorella, Y., Nadalini, A., Wistoff, N., Sa, B., Garofalo, A., Psiakis, R., Tolba, M., Kulmala, A., Limaye, N., Sinanoglu, O., Pinto, S., Palossi, D., Benini, L., Mohammad, B., Rossi, D.

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  17. 17
    Efficient construction of aliasing-free compaction circuitry

    Efficient construction of aliasing-free compaction circuitry by Sinanoglu, O., Orailoglu, A.

    Published in IEEE MICRO
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  18. 18
    Design and analysis of ring oscillator based Design-for-Trust technique

    Design and analysis of ring oscillator based Design-for-Trust technique by Rajendran, J, Jyothi, V, Sinanoglu, O, Karri, R

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  19. 19
    Eliminating Performance Penalty of Scan

    Eliminating Performance Penalty of Scan by Sinanoglu, O.

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  20. 20
    Test power reduction through minimization of scan chain transitions

    Test power reduction through minimization of scan chain transitions by Sinanoglu, O., Bayraktaroglu, I., Orailoglu, A.

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