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Ultra-low power NEMS FPGA
by
Han, Sijing
,
Sirigiri, Vijay
,
Saab, Daniel G.
,
Tabib-Azar, Massood
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Analyzing the effect of dynamic loads on economic dispatch in the presence of interline power flow controller using modified BAT algorithm
by
Vijay Kumar, Y.N.
,
Sivanagaraju, Sirigiri
,
Suresh, Chintalapudi V.
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Journal of Electrical Systems and Information Technology
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Journal Of Electrical Systems And Information Technology
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Applied Computing -- Arts And Humanities -- Architecture -- Computer-Aided Design
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Bridge Circuits
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Cmos Integrated Circuits
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Dynamic Loads
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Interline Power Flow Controller
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Logic Gates
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Modified Bat Algorithm
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