Design Methodology for Voltage-Scaled Clock Distribution Networks by Sitik, Can, Weicheng Liu, Taskin, Baris, Salman, Emre

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SLECTS: Slew-Driven Clock Tree Synthesis by Liu, Weicheng, Sitik, Can, Salman, Emre, Taskin, Baris, Sundareswaran, Savithri, Huang, Benjamin

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Iterative skew minimization for low swing clocks by Sitik, Can, Taskin, Baris

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Timing characterization of clock buffers for clock tree synthesis by Sitik, Can, Lerner, Scott, Taskin, Baris

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FinFET-Based Low-Swing Clocking by Sitik, Can, Salman, Emre, Filippini, Leo, Yoon, Sung Jun, Taskin, Baris

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Enhanced level shifter for multi-voltage operation by Weicheng Liu, Salman, Emre, Sitik, Can, Taskin, Baris

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A microcontroller-based embedded system design course with PSoC3 by Sitik, Can, Nagvajara, Prawat, Taskin, Baris

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Multi-voltage domain clock mesh design by Sitik, C., Taskin, B.

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High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design by Sitik, Can, Filippini, Leo, Salman, Emre, Taskin, Baris

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Determination of Lead, Iron and Nickel in Water and Vegetable Samples after Preconcentration with Aspergillus niger Loaded on Silica Gel by Baytak, Sıtkı, Koçyiǧit, Abdurrahim, Türker, Ali Rehber

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