Search Results - Soh, Lip Kai

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  1. 1
    A low-noise phase-locked loop with programmable gain VCO

    A low-noise phase-locked loop with programmable gain VCO by Lip-Kai Soh

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  2. 2
    A 2.5-12.5Gbps interpolator-based clock and data recovery circuit for FPGA

    A 2.5-12.5Gbps interpolator-based clock and data recovery circuit for FPGA by Lip-Kai Soh, Wai-Tat Wong

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  3. 3
    7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and −58dBc TX HD2

    7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and −58dBc TX HD2 by Yang, Wei, Hu, De Yong, Lam, Chun Kit, Cui, Ji Qing, Soh, Lip Kai, Song, De Cheng, Zhong, Xiao Wei, Hor, Hon Cheong, Heng, Chee Lee

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  4. 4
    Programmable low-dithering-jitter interpolator-based CDR

    Programmable low-dithering-jitter interpolator-based CDR by Lip-Kai Soh, Wai-Tat Wong, Swee-Wah Lee, Chuan-Thim Khor

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  5. 5
    A fast-lock delay-locked loop architecture with improved precharged PFD

    A fast-lock delay-locked loop architecture with improved precharged PFD by Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida

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  6. 6
    Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

    Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector by Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida

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