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Search Results - Somayaji, Jhnanesh
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Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications
by
Kumar, B. Sampath
,
Ajay
,
Paul, Milova
,
Somayaji, Jhnanesh
,
Gossner, Harald
,
Shrivastava, Mayank
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IEEE transactions on electron devices
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Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices
by
Somayaji, Jhnanesh
,
Kumar, B. Sampath
,
Bhat, M. S.
,
Shrivastava, Mayank
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IEEE transactions on electron devices
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Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications
by
Somayaji, B. Jhnanesh
,
Bhat, M. S.
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Ieee Transactions On Electron Devices
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Logic Gates
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