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Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels –An explanation and die protection strategy
by
Sowariraj, M.S.B.
,
Smedes, Theo
,
Salm, Cora
,
Mouthaan, Ton
,
Kuper, Fred G
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Microelectronics and reliability
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A 3-D Circuit Model to evaluate CDM performance of ICs
by
Sowariraj, M.S.B.
,
Smedes, Theo
,
de Jong, Peter C.
,
Salm, Cora
,
Mouthaan, Ton
,
Kuper, Fred G
Published in
Microelectronics and reliability
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The influence of technology variation on ggNMOSTs and SCRs against CDM BSD stress
by
Sowariraj, M.S.B.
,
Salm, Cora
,
Mouthaan, Ton
,
G Kuper, Fred
,
Smedes, Theo
Published in
Microelectronics and reliability
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Significance of including substrate capacitance in the full chip circuit model of ICs under CDM stress
by
Sowariraj, M.S.B.
,
de Jong, P.C.
,
Cora, S.M.
,
Smedes, T.
,
Mouthaan, A.J.T.
,
Kuper, F.G.
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Microelectronics And Reliability
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