Search Results - Stojčev, M.K.

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  1. 1
    A class of fault-tolerant systolic arrays for matrix multiplication

    A class of fault-tolerant systolic arrays for matrix multiplication by MILOVANOVIC, I. Z, MILOVANOVIC, E. I, STOJCEV, M. K

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  2. 2
    Orthogonal fault-tolerant systolic arrays for matrix multiplication

    Orthogonal fault-tolerant systolic arrays for matrix multiplication by Milovanović, I.Ž., Milovanović, E.I., Stojčev, M.K., Bekakos, M.P.

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  3. 3
    Multi-functional systolic array with reconfigurable micro-power processing elements

    Multi-functional systolic array with reconfigurable micro-power processing elements by MILOVANOVIC, E. I, NIKOLIC, T. R, STOJCEV, M. K, MILOVANOVIC, I. Z

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  4. 4
    Address generators for linear systolic array

    Address generators for linear systolic array by STOJCEV, M. K, MILOVANOVIC, I. Z, MILOVANOVIC, E. I, NIKOLIC, T. R

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  5. 5
    A mid-value select voter

    A mid-value select voter by Krstic, M.D., Stojcev, M.K., Djordjevic, G. Lj, Andrejic, I.D.

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  6. 6
    Designing of processor-time optimal systolic arrays for band matrix-vector multiplication

    Designing of processor-time optimal systolic arrays for band matrix-vector multiplication by MILOVANOVIC, I. Z, MILOVANOVIC, E. I, MILENTIJEVIC, I. Z, STOJCEV, M. K

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  7. 7
    Power management and energy harvesting techniques for wireless sensor nodes

    Power management and energy harvesting techniques for wireless sensor nodes by Stojcev, M.K., Kosanovic, M.R., Golubovic, L.R.

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  8. 8
    The asynchronous counterflow pipeline bit-serial multiplier

    The asynchronous counterflow pipeline bit-serial multiplier by TOSIC, M. B, STOJCEV, M. K, MAKSIMOVIC, D. M, DJORDJEVIC, G. L

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  9. 9
    Matrix-vector multiplication on a fixed-size linear systolic array

    Matrix-vector multiplication on a fixed-size linear systolic array by Milovanović, E.I, Stojc̆ev, M.K, Novaković, N.M, Milovanović, I.Z̆, Tokić, T.I

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  10. 10
    The design of optimal planar systolic arrays for matrix multiplication

    The design of optimal planar systolic arrays for matrix multiplication by Milentijević, I.Z., Milovanović, I.Z̆., Milovanović, E.I., Stojc̆ev, M.K.

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  11. 11
    Power Reduction Technique for Successive-Approximation Analog-to-Digital Converters

    Power Reduction Technique for Successive-Approximation Analog-to-Digital Converters by Stankovic, D.B., Stojcev, M.K., Djordjevic, G.L.

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  12. 12
    An optimal scheduling procedure for matrix inversion on linear array at a processor level

    An optimal scheduling procedure for matrix inversion on linear array at a processor level by Stojcev, M K, Milovanovic, E I, Milovanovic, I Z

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  13. 13
    Matrix-vector Multiplication on a Fixed Size Unidirectional Systolic Array

    Matrix-vector Multiplication on a Fixed Size Unidirectional Systolic Array by Stojanovic, N.M., Milovanovic, I.Z., Stojcev, M.K., Milovanovic, E.I.

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  14. 14
    Design of self-checking combinational circuits

    Design of self-checking combinational circuits by Stankovic, T.R., Stojcev, M.K., Djordjevic, G.L.

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  15. 15
    Concurrent error detection in FSMs using transition checking technique

    Concurrent error detection in FSMs using transition checking technique by Djordjevic, G.L., Stankovic, T.R., Stojcev, M.K.

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  16. 16
    Systolic implementation of nonlinear transformation of two sequences

    Systolic implementation of nonlinear transformation of two sequences by Milovanovic, E.I., Milovanovic, I.Z., Randjelovic, B.M., Stojcev, M.K.

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  17. 17
    FPGA implementation of hardware voter

    FPGA implementation of hardware voter by Krstic, M.D., Stojcev, M.K.

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  18. 18
    A hardware mid-value select voter architecture

    A hardware mid-value select voter architecture by Stojcev, M.K., Djordjevic, G.Lj, Krstic, M.D.

    Published in Microelectronics
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  19. 19
    Optimizing AT/sup 2/ measure of hexagonal systolic arrays

    Optimizing AT/sup 2/ measure of hexagonal systolic arrays by Milovanovic, E.I., Stojanovic, N.M., Milovanovic, I.Z., Tokic, T.I., Stojcev, M.K.

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  20. 20
    VHDL-based design of FSM with concurrent error detection capability

    VHDL-based design of FSM with concurrent error detection capability by Stojcev, M.K., Djordjevic, G.L., Stankovic, T.R.

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