Search Results - Stonecypher, W.F.

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  1. 1
    Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

    Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell by Zerbe, J.L., Werner, C.W., Stojanovic, V., Chen, F., Wei, J., Tsang, G., Kim, D., Stonecypher, W.F., Ho, A., Thrush, T.P., Kollipara, R.T., Horowitz, M.A., Donnelly, K.S.

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  2. 2
    A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

    A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers by Zerbe, J.L., Chau, P.S., Werner, C.W., Stonecypher, W.F., Liaw, H.J., Gong Jong Yeh, Thrush, T.P., Best, S.C., Donnelly, K.S.

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  3. 3
    Transition-limiting codes for 4-PAM signaling in high speed serial links

    Transition-limiting codes for 4-PAM signaling in high speed serial links by Bessios, A.G., Stonecypher, W.F., Agarwal, A., Zerbe, J.L.

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  4. 4
    Anatomy of an X terminal

    Anatomy of an X terminal by Socarras, A.E., Cooper, R.S., Stoneycypher, W.F.

    Published in IEEE spectrum
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