A 0.08μm2-sized 8F2 Stack DRAM cell for multi-gigabit DRAM by NOH, Hyunpil, JEONG, Suock, SHIN, Kisoo, LEE, Sangdon, LEE, Seongjoon, KIM, Yousung, CHO, Woncheol, HUH, Min, JEONG, Gucheol, SUH, Jaebuhm, KWEON, Hoyeop, ROH, Jaesung

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A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM by Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, Min Huh, Gucheol Jeong, Jaebuhm Suh, Hoyeop Kweon, Jaesung Roh, Kisoo Shin, Sangdon Lee

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A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM by Hyunpil Noh, Woncheol Cho, Gucheol Jeong, Min Huh, Jaemin Ahn, Ysung Kim, Suock Jeong, Seongjoon Lee, Dongseok Kim, Hazoong Kim, Jaebuhm Suh, Jinwon Park, Sang-don Lee, Hee-koo Yoon

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Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application by Suock Chung, Rho, K.-M, Kim, S.-D, Suh, H.-J, Kim, D.-J, Kim, H.-J, Lee, S.-H, Park, J.-H, Hwang, H.-M, Hwang, S.-M, Lee, J.-Y, An, Y.-B, Yi, J.-U, Seo, Y.-H, Jung, D.-H, Lee, M.-S, Cho, S.-H, Kim, J.-N, Park, G.-J, Gyuan Jin, Driskill-Smith, A, Nikitin, V, Ong, A, Tang, X, Yongki Kim, Rho, J.-S, Park, S.-K, Chung, S.-W, Jeong, J.-G, Hong, S.-J

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