Search Results - Suryagandh, S.

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  1. 1
    A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

    A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs by Suryagandh, S.S., Garg, M., Woo, J.C.S.

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  2. 2
    A detailed analysis of SOI MOSFETs for SOC design

    A detailed analysis of SOI MOSFETs for SOC design by Suryagandh, Garg, Woo

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  3. 3
    Comparison between bulk and SOI MOSFETs for sub-100nm mixed mode applications

    Comparison between bulk and SOI MOSFETs for sub-100nm mixed mode applications by Suryagandh, S.S., Garg, M., Woo, J.C.S.

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  4. 4
    Impact of stress on various circuit characteristics in 65nm PDSOI technology

    Impact of stress on various circuit characteristics in 65nm PDSOI technology by Suryagandh, S., Gupta, M., Zhi-Yuan Wu, Krishnan, S., Pelella, M., Jung-Suk Goo, Thuruthiyil, C., An, J.X., Chen, B.Q., Subba, N., Zamudio, L., Yonemura, J., Icel, A.B.

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  5. 5
    Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs

    Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs by Qiang Chen, Zhi-Yuan Wu, Su, R.Y.K., Jung-Suk Goo, Thuruthiyil, C., Radwin, M., Subba, N., Suryagandh, S., Tran Ly, Wason, V., An, J.X., Icel, A.B.

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  6. 6
    Impact of stress on various circuit characteristics in 65nm PDSOI technology

    Impact of stress on various circuit characteristics in 65nm PDSOI technology by Suryagandh, S., Gupta, M., Zhi-Yuan Wu, Krishnan, S., Pelella, M., Jung-Suk Goo, Thuruthiyil, C., An, J.X., Chen, B.Q., Subba, N., Zamudio, L., Yonemura, J., Icel, A.B.

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  7. 7
    Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications

    Scaling impact on analog performance of sub-100nm MOSFETs for mixed mode applications by Garg, M., Suryagandh, S.S., Woo, J.C.S.

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  8. 8
    Extraction of speculative SOI MOSFET models using self-heating-free targets

    Extraction of speculative SOI MOSFET models using self-heating-free targets by Qiang Chen, Zhi-Yuan Wu, Ly, T., Gupta, M., Wason, V., Jung-Suk Goo, Thuruthiyil, C., Radwin, M., Subba, N., Chiney, P., Suryagandh, S., Icel, A.B.

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  9. 9
    Analog performance of scaled bulk and SOI MOSFETs

    Analog performance of scaled bulk and SOI MOSFETs by Suryagandh, S.S., Garg, M., Gupta, M., Woo, J.C.S.

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  10. 10
    CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

    CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design by Sultan, Akif, Carrejo, Kevin, Meier, Joe, Topaloglu, Rasit O., Chan, Darin, Hahn, Uwe, Knopp, Thorsten, Andrade, Victor, Gardiol, Bill, Hejl, Steve, Wu, David, Faricelli, John, Buller, James, Bair, Larry, Icel, Ali, Apanovich, Yuri, Suryagandh, Sushant, van Meer, Hans, Mathur, Kaveri, Pattison, James, Hannon, Sean, Constant, Greg, Kumar, Kalyana

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