Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion by Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Sze, Cliff N.

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Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes by Davoodi, Azadeh, Hu, Jiang, Ozdal, Mustafa, Sze, Cliff C. N.

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Challenges of cell selection algorithms in industrial high performance microprocessor designs by Reimann, Tiago, Sze, Cliff C.N., Reis, Ricardo

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Gate sizing and threshold voltage assignment for high performance microprocessor designs by Reimann, Tiago, Sze, Cliff C. N., Reis, Ricardo

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Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo by Osiecki, Thomas H., Tsai, Min-yu, Gattiker, Anne E., Jamsek, Damir A., Nassif, Sani R., Speight, W. Evan, Sze, Cliff C.N.

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Clock power minimization using structured latch templates and decision tree induction by Ward, Samuel I., Viswanathan, Natarajan, Zhou, Nancy Y., Sze, Cliff C. N., Zhuo Li, Alpert, Charles J., Pan, David Z.

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The DAC 2012 routability-driven placement contest and benchmark suite by Viswanathan, Natarajan, Alpert, Charles, Sze, Cliff, Li, Zhuo, Wei, Yaoguang

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GLARE: global and local wiring aware routability evaluation by Wei, Yaoguang, Sze, Cliff, Viswanathan, Natarajan, Li, Zhuo, Alpert, Charles J., Reddy, Lakshmi, Huber, Andrew D., Tellez, Gustavo E., Keller, Douglas, Sapatnekar, Sachin S.

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ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite by Viswanathan, Natarajan, Alpert, Charles, Sze, Cliff, Li, Zhuo, Wei, Yaoguang

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