Search Results - TERASHIMA, Tomohide

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  1. 1
    High-Voltage Integrated Circuits: History, State of the Art, and Future Prospects

    High-Voltage Integrated Circuits: History, State of the Art, and Future Prospects by Disney, Don, Letavic, Ted, Trajkovic, Tanya, Terashima, Tomohide, Nakagawa, Akio

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  2. 2
    Characterization and Modeling of a 1.2-kV 30-A Silicon-Carbide MOSFET

    Characterization and Modeling of a 1.2-kV 30-A Silicon-Carbide MOSFET by Mukunoki, Yasushige, Nakamura, Yuta, Horiguchi, Takeshi, Kinouchi, Shin-ichi, Nakayama, Yasushi, Terashima, Tomohide, Kuzumoto, Masaki, Akagi, Hirofumi

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  3. 3
    An Analytical Evaluation of Performance Limit for PiN diodes and IGBTs

    An Analytical Evaluation of Performance Limit for PiN diodes and IGBTs by Terashima, Tomohide

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  4. 4
    An analytical calculation for lowest forward voltage of PiN diodes

    An analytical calculation for lowest forward voltage of PiN diodes by Terashima, Tomohide

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  5. 5
    Great impact of RFC technology on fast recovery diode towards 600 V for low loss and high dynamic ruggedness

    Great impact of RFC technology on fast recovery diode towards 600 V for low loss and high dynamic ruggedness by Masuoka, F., Nakamura, K., Nishii, A., Terashima, T.

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  6. 6
    Development of secured energy infrastructure in Japan

    Development of secured energy infrastructure in Japan by Yamamoto, Masazumi, Terashima, Tomohide

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  7. 7
    A novel driving technology for a passive gate on a Lateral-IGBT

    A novel driving technology for a passive gate on a Lateral-IGBT by Terashima, T.

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  8. 8
    A balanced High Voltage IGBT design with ultra dynamic ruggedness and area-efficient edge termination

    A balanced High Voltage IGBT design with ultra dynamic ruggedness and area-efficient edge termination by Ze Chen, Nakamura, Katsumi, Nishii, Akito, Terashima, Tomohide, Kawakami, Tsuyoshi

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  9. 9
    LPT(II)-CSTBT™(III) for High Voltage application with ultra robust turn-off capability utilizing novel edge termination design

    LPT(II)-CSTBT™(III) for High Voltage application with ultra robust turn-off capability utilizing novel edge termination design by Ze Chen, Nakamura, K., Terashima, T.

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  10. 10
    Next generation 600V CSTBT™ with an advanced fine pattern and a thin wafer process technologies

    Next generation 600V CSTBT™ with an advanced fine pattern and a thin wafer process technologies by Honda, S., Haraguchi, Y., Narazaki, A., Terashima, T., Terasaki, Y.

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  11. 11
    The 2nd Generation divided RESURF structure for High Voltage ICs

    The 2nd Generation divided RESURF structure for High Voltage ICs by Shimizu, K., Terashima, T.

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  12. 12
    Relaxation of current filament due to RFC technology and ballast resistor for robust FWD operation

    Relaxation of current filament due to RFC technology and ballast resistor for robust FWD operation by Nishii, A., Nakamura, K., Masuoka, F., Terashima, T.

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  13. 13
    Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition

    Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition by Soneda, Shinya, Narazaki, A., Takahashi, T., Takano, K., Kido, S., Fukada, Y., Taguchi, K., Terashima, T.

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  14. 14
    CSTBT™(III) having wide SOA under high temperature condition

    CSTBT™(III) having wide SOA under high temperature condition by Fukada, Y., Suzuki, K., Takahashi, T., Harada, T., Fujii, H., Ishizawa, S., Yamashita, J., Donlon, J. F., Terashima, T.

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  15. 15
    Configuration of JI-LIGBT for Over 100 kHz Switching

    Configuration of JI-LIGBT for Over 100 kHz Switching by Terashima, T., Moritani, J.

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  16. 16
    Trench-Isolated High-Voltage IC with Reduced Parasitic Bipolar Transistor Action

    Trench-Isolated High-Voltage IC with Reduced Parasitic Bipolar Transistor Action by Takahashi, T., Terashima, T., Moritani, J.

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  17. 17
    High speed lateral-IGBT with a passive gate

    High speed lateral-IGBT with a passive gate by Terashima, T., Moritani, J.

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  18. 18
    An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI

    An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI by Watabe, K., Akiyama, H., Terashima, T., Okada, M., Nobuto, S., Yamawaki, M., Asai, S.

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  19. 19
    120 V BiC-DMOS process for the latest automotive and display applications

    120 V BiC-DMOS process for the latest automotive and display applications by Terashima, T., Yamamoto, F., Hatasako, K., Hine, S.

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  20. 20
    120V BiC-DMOS process for the latest automotive and display applications

    120V BiC-DMOS process for the latest automotive and display applications by TERASHIMA, Tomohide, YAMAMOTO, Fumitoshi, HATASAKO, Kenichi, HINE, Shiro

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