WLCSP Package and PCB Design for Board Level Reliability by Chiu, Jason, Chang, K.C., Hsu, Steven, Tsao, Pei-Haw, Lii, M.J.

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Investigation of charge induced bond pad corrosion by Pei-Haw Tsao, Hung-Yu Chiu, Liao, H. C., Chen, K. C., Sung, M. C., Chen, Worth, Antai Xu

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Low-K Flip Chip Board Level Reliability on 65nm Technology by Pei-Haw Tsao, Bill Kiang, Wu, K., Abel Chang, Tsomg-Dih Yuan

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Underfill characterization for low-k dielectric / Cu interconnect IC flip-chip package reliability by TSAO, Pei-Haw, HUANG, Chender, LII, Mirng-Ji, SU, Bob, TSAI, Nun-Sian

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Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric / Cu interconnects IC by TSAO, Pei-Haw, HUANG, Chender, LIN, Allan, LII, Mimg-Ji, PERNG, D. J, TSAI, Nun-Sian

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Board Level Reliability Enhancement of WLCSP with Large Chip Size by Tsao, P. H., Lu, T. H., Chen, T. M., Chang, K. C., Kuo, C. M., Lii, M. J., Chu, L. H.

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Manufacturing stresses in die due to die attach process by Pei-Haw Tsao, Voloshin, A.S.

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Analysis of the stresses in the chip's coating by Voloshin, A.S., Pei-Haw Tsao

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Manufacturing stresses in the die due to the die-attach process by Tsao, P.-H., Voloshin, A.S.

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Effects of assembly methodology on manufacturing-induced stresses in /spl mu/BGA packages by Pei-Haw Tsao, Chun-Liang Chen, Yu-Jen Huang, Chender Huang

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