Search Results - Takauchi, Toshihiko

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  1. 1
    Parallel voltage sag compensator with reduced capacitance using a boost-type power factor correction rectifier

    Parallel voltage sag compensator with reduced capacitance using a boost-type power factor correction rectifier by Kojima, Tetsuya, Takauchi, Toshihiko, Ise, Toshifumi, Iyoda, Isao, Kono, Yoshiyuki, Temma, Koji, Sasao, Hiroyuki, Yamasaki, Kiyomi, Inoue, Nobuyoshi, Takeuchi, Yasunori

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  2. 2
    A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

    A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE by Oishi, Kazuaki, Yoshida, Eiji, Sakai, Yasufumi, Takauchi, Hideki, Kawano, Yoichi, Shirai, Noriaki, Kano, Hideki, Kudo, Masahiro, Murakami, Tomotoshi, Tamura, Tetsuro, Kawai, Shigeaki, Suto, Kazuo, Yamazaki, Hiroshi, Mori, Toshihiko

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  3. 3
    A CMOS multichannel 10-Gb/s transceiver

    A CMOS multichannel 10-Gb/s transceiver by Takauchi, H., Tamura, H., Matsubara, S., Kibune, M., Doi, Y., Chiba, T., Anbutsu, H., Yamaguchi, H., Mori, T., Takatsu, M., Gotoh, K., Sakai, T., Yamamura, T.

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  4. 4
    A 56-Gb/s Wireline Transceiver in 20nm CMOS

    A 56-Gb/s Wireline Transceiver in 20nm CMOS by Shibasaki, Takayuki, Yanfei Chen, Yoshiyasu Doi, Takauchi, Hideki, Mori, Toshihiko, Koyanagi, Yoichi, Tamura, Hirotaka

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  5. 5
    3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE

    3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE by Oishi, Kazuaki, Yoshida, Eiji, Sakai, Yasufumi, Takauchi, Hideki, Kawano, Yoichi, Shirai, Noriaki, Kano, Hideki, Kudo, Masahiro, Murakami, Tomotoshi, Tamura, Tetsuro, Kawai, Shigeaki, Yamaura, Shinji, Suto, Kazuo, Yamazaki, Hiroshi, Mori, Toshihiko

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  6. 6
    A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

    A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS by Shibasaki, Takayuki, Chaivipas, Win, Yanfei Chen, Doi, Yoshiyasu, Hamada, Takayuki, Takauchi, Hideki, Mori, Toshihiko, Koyanagi, Yoichi, Tamura, Hirotaka

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