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IBM POWER6 accelerators: VMX and DFU
by
Eisen, L.
,
Ward, J. W.
,
Tast, H.-W.
,
Mading, N.
,
Leenstra, J.
,
Mueller, S. M.
,
Jacobi, C.
,
Preiss, J.
,
Schwarz, E. M.
,
Carlough, S. R.
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IBM journal of research and development
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Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods
by
Krautz, U.
,
Pflanz, M.
,
Jacobi, C.
,
Tast, H.W.
,
Weber, K.
,
Vierhaus, H.T.
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IBM POWER6 accelerators : VMX and DFU: IBM POWER6 Microprocessor Technology
by
EISEN, L
,
WARD, J. W
,
TAST, H.-W
,
MÄDING, N
,
LEENSTRA, J
,
MUELLER, S. M
,
JACOBI, C
,
PREISS, J
,
SCHWARZ, E. M
,
CARLOUGH, S. R
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IBM journal of research and development
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Array Processors
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Binary Decision Diagrams
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Circuit Faults
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