Search Results - Teifel, John

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  1. 1
    Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation

    Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation by Teifel, J.

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  2. 2
    An asynchronous dataflow FPGA architecture

    An asynchronous dataflow FPGA architecture by Teifel, J., Manohar, R.

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  3. 3
    Using MRED to Screen Multiple-Node Charge-Collection Mitigated SOI Layouts

    Using MRED to Screen Multiple-Node Charge-Collection Mitigated SOI Layouts by Black, Jeffrey D., Dame, Jeff A., Black, Dolores A., Dodd, Paul E., Shaneyfelt, Marty R., Teifel, John, Salas, Joseph G., Steinbach, Robert, Davis, Matthew, Reed, Robert A., Weller, Robert A., Trippe, James M., Warren, Kevin M., Tonigan, Andrew M., Schrimpf, Ronald D., Marquez, Richard S.

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  4. 4
    Asynchronous Cryptographic Hardware Design

    Asynchronous Cryptographic Hardware Design by Teifel, J.

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  5. 5
    Using MRED to Screen Multiple Node Charge Collection Mitigated SOI Layouts

    Using MRED to Screen Multiple Node Charge Collection Mitigated SOI Layouts by Black, Jeffrey, Dame, Jeff A., Black, Dolores Archuleta, Dodd, Paul E., Shaneyfelt, Marty R., Teifel, John, Salas, Joseph Gregory, Steinbach, Robert, Davis, Matthew, Reed, Robert A., Weller, Robert A., Trippe, James, Warren, Kevin M., Tonigan, Andrew M., Schrimpf, Ronald D., Marquez, Richard S.

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  6. 6
    ViArray standard platforms: Rad-hard structured ASICs for digital and mixed-signal applications

    ViArray standard platforms: Rad-hard structured ASICs for digital and mixed-signal applications by Teifel, J., Flores, R. S., Pearson, S., Begay, C., Kwok Kee Ma, Palmer, J.

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  7. 7
    Static tokens: using dataflow to automate concurrent pipeline synthesis

    Static tokens: using dataflow to automate concurrent pipeline synthesis by Teifel, J., Manohar, R.

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  8. 8
    A high-speed clockless serial link transceiver

    A high-speed clockless serial link transceiver by Teifel, J., Manohar, R.

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  9. 9
    A quick-turn 3D structured ASIC platform for cost-sensitive applications

    A quick-turn 3D structured ASIC platform for cost-sensitive applications by Teifel, John, Flores, Richard S., Jarecki, Robert, Bauer, Todd, Shinde, Subhash L.

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  10. 10
    A high-performance asynchronous FPGA: test results

    A high-performance asynchronous FPGA: test results by Fang, D., Teifel, J., Rajit Manohar

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