Comparison of parallel central processing unit‐ and graphics processing unit‐based implementations of greedy string tiling algorithm for source code plagiarism detection by Mišić, Marko J., Tomašević, Milo V.

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Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture by Radulović, Milan B., Girbal, Sylvain, Tomašević, Milo V.

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Use case analysis of OpenACC directives in the implementation of image processing algorithms by Misic, Marko J., Dasic, Darija D., Tomasevic, Milo V.

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Towards an Improved Integrated Coherence and Speculation Protocol by Radulovic, M.B., Tomasevic, M.V.

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An Aggressive Register-level Communication in a Speculative Chip Multiprocessor by Radulovic, M.B., Tomasevic, M.V.

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Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1 by Tomasevic, M., Milutinovic, V.

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Balancing between time and memory requirements in cryptanalysis by Tomasevic, V., Tomasevic, M.

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The word-invalidate cache coherence protocol by Tomasevic, M, Milutinovic, V

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An operating system accelerator by DJORDJEVIC, J, TOMASEVIC, M, BOJOVIC, M, POTIC, V, RANDJIC, S

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Improved RMS for the PC environment by Savić, Savo, Tomašević, Milo, Milutinović, Veljko, Gupta, Anil, Natale, Mark, Gertner, Ilya

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Distributed shared memory: concepts and systems by Protic, J., Tomasevic, M., Milutinovic, V.

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A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors by Tomasevic, M., Milutinovic, V.

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A simulation study of hardware-oriented DSM approaches by Grujic, A., Tomasevic, M., Milutinovic, V.

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