A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface by Tyhach, J., Wang, B., Sung, C., Huang, J., Nguyen, K., Xiaobao Wang, Yan Chong, Pan, P., Kim, H., Rangan, G., Tzung-Chin Chang, Tan, J.

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Robust position control of a transportation carriage directly driven by linear motor using wavelet neural by Shieh, Niahn-Chung, Chang, Chin-Tzung, Lin, Chun-Liang, Jan, Horn-Yong

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A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface by Tyhach, J., Wang, B., Chiakang Sung, Huang, J., Nguyen, K., Xiaobao Wang, Yan Chong, Pan, P., Kim, H., Rangan, G., Tzung-Chin Chang, Tan, J.

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Formation of porous poly(vinylidene fluoride) membranes with symmetric or asymmetric morphology by immersion precipitation in the water/TEP/PVDF system by Lin, Dar-Jong, Chang, Hsu-Hsien, Chen, Tzung-Chin, Lee, Yi-Chi, Cheng, Liao-Ping

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A 90nm FPGA I/O buffer design with 1.6Gbps data rate for source-synchronous system and 300MHz clock rate for external memory interface by TYHACH, Jeffrey, WANG, Bonnie, CHANG, Tzung-Chin, TAN, Johnson, SUNG, Chiakang, HUANG, Joseph, NGUYEN, Khai, XIAOBAO WANG, YAN CHONG, PAN, Philip, KIM, Henry, RANGAN, Gopinath

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Fine structure of poly(vinylidene fluoride) membranes prepared by phase inversion from a water/N-methyl-2-pyrollidone/poly(vinylidene fluoride) system by Lin, Dar-Jong, Chang, Cheng-Liang, Chang, Chi-Lin, Chen, Tzung-Chin, Cheng, Liao-Ping

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Microporous PVDF membrane formation by immersion precipitation from water/TEP/PVDF system by Lin, Dar-Jong, Chang, Cheng-Liang, Chen, Tzung-Chin, Cheng, Liao-Ping

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