Search Results - Umai, Seiichi

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  1. 1
    A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link

    A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link by Ono, G., Watanabe, K., Muto, T., Yamashita, H., Fukuda, K., Masuda, N., Nemoto, R., Suzuki, E., Takemoto, T., Yuki, F., Yagyu, M., Toyoda, H., Kono, M., Kambe, A., Umai, S., Saito, T., Nishimura, S.

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  2. 2
    A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link

    A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link by Fukuda, K., Ono, G., Watanabe, K., Muto, T., Yamashita, H., Masuda, N., Nemoto, R., Suzuki, E., Takemoto, T., Yuki, F., Yagyu, M., Toyoda, H., Kono, M., Kambe, A., Umai, S., Saito, T., Nishimura, S.

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  3. 3
    3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

    3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS by Norimatsu, Takayasu, Kawamoto, Takashi, Kogo, Kenji, Kohmu, Naohiro, Yuki, Fumio, Nakajima, Norio, Muto, Takashi, Nasu, Junya, Komori, Takemasa, Koba, Hideki, Usugi, Tatsunori, Hokari, Tomofumi, Kawamata, Tsuneo, Ito, Yuichi, Umai, Seiichi, Tsuge, Masatoshi, Yamashita, Takeo, Hasegawa, Masatoshi, Higeta, Keiichi

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  4. 4
    3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

    3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS by Kawamoto, Takashi, Norimatsu, Takayasu, Kogo, Kenji, Yuki, Fumio, Nakajima, Norio, Tsuge, Masatoshi, Usugi, Tatsunori, Hokari, Tomofumi, Koba, Hideki, Komori, Takemasa, Nasu, Junya, Kawamata, Tsuneo, Ito, Yuichi, Umai, Seiichi, Kumazawa, Jun, Kurahashi, Hiroaki, Muto, Takashi, Yamashita, Takeo, Hasegawa, Masatoshi, Higeta, Keiichi

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  5. 5
    3.2 multi-standard 185fs sub(rms) 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

    3.2 multi-standard 185fs sub(rms) 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS by Kawamoto, Takashi, Norimatsu, Takayasu, Kogo, Kenji, Yuki, Fumio, Nakajima, Norio, Tsuge, Masatoshi, Usugi, Tatsunori, Hokari, Tomofumi, Koba, Hideki, Komori, Takemasa, Nasu, Junya, Kawamata, Tsuneo, Ito, Yuichi, Umai, Seiichi, Kumazawa, Jun, Kurahashi, Hiroaki, Muto, Takashi, Yamashita, Takeo, Hasegawa, Masatoshi, Higeta, Keiichi

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