Search Results - Uppugunduru, Anil Kumar

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  1. 1
    ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks

    ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks by Jonnalagadda, Aditya Anirudh, Kumar, Uppugunduru Anil, Thotli, Rishi, Sardesai, Satvik, Veeramachaneni, Sreehari, Ahmed, Syed Ershad

    Published in IEEE access
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  2. 2
    Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation

    Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation by Anil Kumar, Uppugunduru, Guturu, Sahith, Ahmed, Syed Ershad

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  3. 3
    A Power-Efficient Gaussian Filter Architecture Using Adder Compressors for Edge Detection Application

    A Power-Efficient Gaussian Filter Architecture Using Adder Compressors for Edge Detection Application by Guturu, Sahith, Uppugunduru, Anil Kumar, Sharma, Apoorva, Ahmed, Syed Ershad

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  4. 4
    Energy-Efficient Ternary Multiplier

    Energy-Efficient Ternary Multiplier by Agrawal, Rishi, Abhijith, Narayanabhatla Savyasachi, Anil Kumar, Uppugunduru, Veeramachaneni, Sreehari, Ahmed, Syed Ershad

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  5. 5
    Hardware-efficient approximate multiplier architectures for media processing applications

    Hardware-efficient approximate multiplier architectures for media processing applications by Uppugunduru, Anil Kumar, Ahmed, Syed Ershad

    Published in Circuit world
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  6. 6
    Design methodology for highly accurate approximate multipliers for error resilient applications

    Design methodology for highly accurate approximate multipliers for error resilient applications by Guturu, Sahith, Kumar, Uppugunduru Anil, Bharadwaj, S. Vignesh, Ahmed, Syed Ershad

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  7. 7
    Compressor based hybrid approximate multiplier architectures with efficient error correction logic

    Compressor based hybrid approximate multiplier architectures with efficient error correction logic by Uppugunduru, Anil Kumar, Vignesh Bharadwaj, S., Ahmed, Syed Ershad

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  8. 8
    Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic

    Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic by Jonnalagadda, Aditya Anirudh, Thotli, Rishi, Veeramachaneni, Sreehari, Kumar, Uppugunduru Anil, Ahmed, Syed Ershad

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