Search Results - Vallepalli, N.

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  1. 1
    A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

    A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply by Kevin Zhang, Bhattacharya, U., Zhanping Chen, Hamzaoglu, F., Murray, D., Vallepalli, N., Yih Wang, Bo Zheng, Bohr, M.

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  2. 2
    SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

    SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction by Zhang, K., Bhattacharya, U., Zhanping Chen, Hamzaoglu, F., Murray, D., Vallepalli, N., Yih Wang, Zheng, B., Bohr, M.

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  3. 3
    A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

    A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply by Zhang, K., Bhattacharya, U., Chen, Z., Hamzaoglu, F., Murray, D., Vallepalli, N., Wang, Y., Zheng, B., Bohr, M.

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