Search Results - Vamvakos, Socrates

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  1. 1
    ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

    ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET by Lin, Haidang, Boecker, Charlie, Hossain, Masum, Tangirala, Shankar, Vu, Roxanne, Vamvakos, Socrates D., Groen, Eric, Li, Simon, Choudhary, Prashant, Wang, Nanyan, Shibata, Masumi, Taghavi, Hossein, van Ierssel, Marcus, Maniyar, AdilHussain, Wodkowski, Adam, Brar, Kulwant, Nguyen, Nhat, Desai, Shaishav

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  2. 2
    10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture

    10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture by Groen, Eric, Boecker, Charlie, Hossain, Masum, Vu, Roxanne, Vamvakos, Socrates D., Lin, Haidang, Li, Simon, Van Ierssel, Marcus, Choudhary, Prashant, Wang, Nanyan, Shibata, Masumi, Taghavi, Mohammad Hossein, Brar, Kulwant, Nguyen, Nhat, Desai, Shaishav

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  3. 3
    Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

    Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences by Waheed, K., Staszewski, R. B., Dulger, F., Ullah, M. S., Vamvakos, S. D.

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  4. 4
    An Intelligent RAM with Serial I/Os

    An Intelligent RAM with Serial I/Os by Kleveland, Bendik, Miller, Michael John, David, Ronald B., Patel, Jay, Chopra, Rajesh, Sikdar, Dipak K., Kumala, Jeff, Vamvakos, Socrates D., Morrison, Mike, Liu, Ming, Balachandran, Jayaprakash

    Published in IEEE MICRO
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  5. 5
    Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis

    Discrete-Time, Linear Periodically Time-Variant Phase-Locked Loop Model for Jitter Analysis by Vamvakos, S D, Stojanovic, V, Nikolic, B

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  6. 6
    6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET

    6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET by Groen, Eric, Boecker, Charlie, Hossain, Masum, Vu, Roxanne, Vamvakos, Socrates, Lin, Haidang, Li, Simon, Van Ierssel, Marcus, Choudhary, Prashant, Wang, Nanyan, Shibata, Masumi, Taghavi, Mohammad Hossein, Nguyen, Nhat, Desai, Shaishav

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  7. 7
    A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

    A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications by Vamvakos, Socrates D., Gauthier, Claude R., Rao, Chethan, Wang, Alvin, Canagasaby, Karthisha Ramoshan, Abugharbieh, Khaldoon, Choudhary, Prashant, Dabral, Sanjay, Desai, Shaishav, Hassan, Mahmudul, Hsieh, K. C., Kleveland, Bendik, Mandal, Gurupada, Rouse, Richard, Saraf, Ritesh, Yeung, Jason, Cao, Ying

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  8. 8
    A 2.488a11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

    A 2.488a11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications by Vamvakos, Socrates, Gauthier, Claude, Rao, Chethan, Wang, Alvin, Canagasaby, Karthisha, Abugharbieh, Khaldoon, Choudhary, Prashant, Dabral, Sanjay, Desai, Shaishav, Hassan, Mahmudul, Hsieh, K, Kleveland, Bendik, Mandal, Gurupada, Rouse, Richard, Saraf, Ritesh, Yeung, Jason, Cao, Ying

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  9. 9
    A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

    A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop by Vamvakos, Socrates D., Boecker, Charles, Groen, Eric, Wang, Alvin, Desai, Shaishav, Irwin, Scott, Rao, Vithal, Bottelli, Aldo, Jawji Chen, Xiaole Chen, Choudhary, Prashant, Kuo-Chiang Hsieh, Jennings, Paul, Haidang Lin, Dan Pechiu, Rao, Chethan, Yeung, Jason

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  10. 10
    Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator

    Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator by Vamvakos, Socrates D, Jingcheng Zhuang, Waheed, Khurram

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  11. 11
    Noise Analysis of Time-to-Digital Converter in All-Digital PLLs

    Noise Analysis of Time-to-Digital Converter in All-Digital PLLs by Vamvakos, S.D., Bogdan Staszewski, R., Sheba, M., Waheed, K.

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  12. 12
    Spurious free time-to-digital conversion in an ADPLL using short dithering sequences

    Spurious free time-to-digital conversion in an ADPLL using short dithering sequences by Waheed, K, Sheba, M, Staszewski, R B, Dulger, F, Vamvakos, S D

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  13. 13
    A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

    A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications by Vamvakos, S. D., Gauthier, C. R., Rao, Chethan, Canagasaby, K. R., Choudhary, P., Dabral, S., Desai, S., Hassan, M., Hsieh, K. C., Kleveland, B., Mandal, G., Rouse, R., Saraf, R., Wang, A., Yeung, J., Abugharbieh, K., Ying Cao

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  14. 14
    Discrete-time, cyclostationary phase-locked loop model for jitter analysis

    Discrete-time, cyclostationary phase-locked loop model for jitter analysis by Vamvakos, S.D., Stojanovic, V., Nikolic, B.

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  15. 15
    A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET

    A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET by Lin, Haidang, Boecker, Charles, Hossain, Masum, Tangirala, Shankar, Vu, Roxanne, Vamvakos, Socrates, Groen, Eric, Li, Simon, Choudhary, Prashant, Wang, Nanyan, Shibata, Masumi, Taghavi, Hossein, van Ierssel, Marcus, Maniyar, AdilHussain, Wodkowski, Adam, Nguyen, Nhat, Desai, Shaishav

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  16. 16
    PLL On-Chip Jitter Measurement: Analysis and Design

    PLL On-Chip Jitter Measurement: Analysis and Design by Vamvakos, S.D., Stojanovic, V., Zerbe, J.L., Werner, C.W., Draper, D., Nikolic, B.

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