Heterogeneous multiprocessor for the management of real-time video and graphics streams by Strik, M.T.J., Timmer, A.H., van Meerbergen, J.L., van Rootselaar, G.-J.

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Constraint analysis for DSP code generation by Mesman, B., Timmer, A.H., Van Meerbergen, J.L., Jess, J.A.G.

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Improved force-directed scheduling in high-throughput digital signal processing by Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L., Korst, J.H.M., van Meerbergen, J.L., van der Werf, A.

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A video display processing platform for future TV concepts by de With, P.H.N., Jaspers, E.G.T., van Meerbergen, J.L., Timmer, A.H., Strik, T.J.

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Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms by De Man, H., Catthoor, F., Goossens, G., Vanhoof, J., Van Meerbergen, J.L., Note, S., Huisken, J.A.

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The complexity of multidimensional periodic scheduling by Verhaegh, W.F.J., Lippens, P.E.R., Aarts, E.H.L., van Meerbergen, J.L., van der Werf, A.

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Stream communication between real-time tasks in a high-performance multiprocessor by Leijten, J.A.J., van Meerbergen, J.L., Timmer, A.H., Jess, J.A.G.

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A constraint driven approach to loop pipelining and register binding by Mesman, B., Strik, M., Timmer, A.H., van Meerbergen, J.L., Jess, J.A.G.

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Consumer applications: a driving force for high-level synthesis of signal-processing architectures by Woudsma, R., van Meerbergen, J.L.

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A 256-point discrete Fourier transform processor fabricated in a 2 /spl mu/m NMOS technology by van Meerbergen, J.L., van Wyk, F.J.

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Measurement of the minority-carrier transport parameters in heavily doped silicon by Mertens, R.P., Van Meerbergen, J.L., Nijs, J.F., Van Overstraeten, R.J.

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PROPHID: a heterogeneous multi-processor architecture for multimedia by Leijten, J.A.J., van Meerbergen, J.L., Timmer, A.H., Jess, J.A.G.

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Applying the adder inverting property in the design of cost-efficient reconfigurable logic by Leijten-Nowak, K., van Meerbergen, J.L.

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A video display processing platform for future TV concepts by De With, P.H.N., Jaspers, E.G.T., Timmer, A.H., Van Meerbergen, J.L.

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Memory synthesis for high speed DSP applications by Lippens, P.E.R., van Meerbergen, J.L., van der Werf, A., Verhaegh, W.F.J., McSweeney, B.T.

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A 2-/spl mu/m CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank by Welten, F.P.J.M., Delaruelle, A., Van Wyk, F.J., Van Meerbergen, J.L., Schmid, J., Rinner, K., Van Eerdewijk, K.J.E., Wittek, J.H.

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A 2-μm CMOS 8-MIPS digital processor with parallel processing capability by Van Wijk, F.J., van Meerbergen, J.L., Welten, F.P., Stoter, J., Huisken, J.A., Delaruelle, A., van Eerdewijk, K.J.E., Schmid, J., Wittek, J.H.

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A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability by Van Wijk, F.J., van Meerbergen, J.L., Welten, F.P., Stoter, J., Huisken, J.A., Delaruelle, A., van Eerdewijk, K.J.E., Schmid, J., Wittek, J.H.

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PROPHID: a data-driven multi-processor architecture for high-performance DSP by Leijten, J.A.J., van Meerbergen, J.L., Timmer, A.H., Jess, J.A.G.

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Guaranteeing on- and off-chip communication in embedded systems by Timmer, A.H., Harmsze, F.J., Leijten, J.A.J., Strik, M.T.J., Van Meerbergen, J.L.

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