Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs) by Hyoung Joon Kim, Ser Choong Chong, Ho, D. S. W., Yong, E. W. Y., Chee Houe Khong, Teo, C. W. L., Fernandez, D. M., Guan Kian Lau, Vasarla, N. S., Lee, V. W. S., Vempati, S. R., Navas, K. O. K.

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Solder joint encapsulation and reliability using dippable underfill by Yen Chen Yeo, Huang, M, Fa Xing Che, Ser Choong Chong, Lim, K C S, Thew, S, Vasarla, N S, Shan Gao

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Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects by Aibin Yu, Lau, J. H., Soon Wee Ho, Kumar, A., Wai Yin Hnin, Wen Sheng Lee, Ming Ching Jong, Sekhar, V. N., Kripesh, V., Pinjala, D., Chen, S., Chien-Feng Chan, Chun-Chieh Chao, Chi-Hsin Chiu, Chih-Ming Huang, Chen, C.

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Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-k Stack by Sekhar, V. N., Lu Shen, Kumar, A., Tai Chong Chai, Xiaowu Zhang, Premchandran, C. S., Kripesh, V., Seung Wook Yoon, Lau, J. H.

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Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages by Sharma, G, Rao, V S, Kumar, A, Lim Ying Ying, Khong Chee Houe, Lim, S, Sekhar, V N, Rajoo, R, Kripesh, V, Lau, J H

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Process and Reliability of Embedded Micro-Wafer-Level Package (EMWLP) Using Low Cure Temperature Dielectric Material by Rao, V. S., Sekhar, V. N., Ho Soon Wee, Rajoo, R., Sharma, G., Lim Ying Ying, Damaruganath, P.

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Development of a Cu/Low- k Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications by Xiaowu Zhang, Lau, J H, Premachandran, C S, Ser-Choong Chong, Leong Ching Wai, Lee, V, Chai, T C, Kripesh, V, Sekhar, V N, Pinjala, D, Che, F X

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Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package by Yue Ying Ong, Soon Wee Ho, Sekhar, V N, Xuefen Ong, Ong, J, Xiaowu Zhang, Vaidyanathan, K, Seung Uk Yoon, Lau, J H, Lim Yeow Kheng, Yeo, D, Kai Chong Chan, Yanfeng Zhang, Juan Boon Tan, Dong Kyun Sohn

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Impact of Packaging Design on Reliability of Large Die Cu/Low- \kappa (BD) Interconnect by Chai, T. C., Zhang, X., Li, H. Y., Sekhar, V. N., Khan, O. K. N., Lau, J., Murthy, R., Yeow Meng Tan, Cheng, C. K., Siao Li Liew, Dongzhi Chi

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Embedded wafer level packages with laterally placed and vertically stacked thin dies by Sharma, G., Rao, V.S., Kumar, A., Su, N., Lim Ying Ying, Khong Chee Houe, Lim, S., Sekhar, V.N., Rajoo, R., Kripesh, V., Lau, J.H.

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Challenges and approaches of TSV thin die stacking on organic substrate by Pei-Siang, S. L., Che Faxing, Chong Ser Choong, Rong, M. C. B., Sekhar, V. N., Rao, V. S., Chai Tai Chong

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Embedding of 15um thin chip and passives in thin flexible substrate by Rajoo, Ranjan, Lim, Y Y, Chong, S C, Myo Paing, Moses, F D, Hong, Justin See Toh Wai, Sekhar, V N, Soon Wee Ho, Thew, S, Soon, Justin Wee Kim, Xiaowu Zhang

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