Experimental evidence of TBD power-law for voltage dependence of oxide breakdown in ultrathin gate oxides by Wu, E.Y, Vayshenker, A, Nowak, E, Sune, J, Vollertsen, R.-P, Lai, W, Harmon, D

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Voltage dependence of hard breakdown growth and the reliability implication in thin dielectrics by Linder, B.P., Lombardo, S., Stathis, J.H., Vayshenker, A., Frank, D.J.

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“As soon as people hear that word…”: associative stigma among clinicians working with people with serious mental illness by Vayshenker, Beth A, DeLuca, Joseph, Bustle, Timothy, Yanos, Philip

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Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides by Wu, E, Suñé, J, Lai, W, Nowak, E, McKenna, J, Vayshenker, A, Harmon, D

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Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs by Kerber, A, Vayshenker, A, Lipp, D, Nigam, T, Cartier, E

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CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics by Wu, E Y, Nowak, E J, Vayshenker, A, Lai, W L, Harmon, D L

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Critical reliability challenges in scaling SiO2-based dielectric to its limit by Wu, E.Y., Suñé, J., Lai, W., Vayshenker, A., Nowak, E., Harmon, D.

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Gate oxide breakdown under Current Limited Constant Voltage Stress by Linder, B.P., Stathis, J.H., Wachnik, R.A., Wu, E., Cohen, S.A., Ray, A., Vayshenker, A.

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The effect of change of voltage acceleration on temperature activation of oxide breakdown for ultrathin oxides by Wu, E.Y., McKenna, J.M., Lai, W., Nowak, E., Vayshenker, A.

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Self-heating characterization and its applications in technology development by Paliwoda, P., Toledano-Luque, M., Nigam, T., Guarin, F., Nour, M., Cimino, S., Pantisano, L., Gupta, A., Gonzalez, O. H., Hauser, M., Liu, W., Vayshenker, A., Ioannou, D., Lee, D., Jiang, L., Yee, P., Rauch, S., Min, B.

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Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin oxides by Wu, E, Suñé, J, Lai, W, Nowak, E, McKenna, J, Vayshenker, A, Harmon, D

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Experimental evidence of T/BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides by Wu, E Y, Vayshenker, A, Nowak, E, Sune, J, Vollertsen, R-P, Lai, W, Harmon, D

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High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing by Chudzik, M., Doris, B., Mo, R., Sleight, J., Cartier, E., Dewan, C., Park, D., Bu, H., Natzle, W., Yan, W., Ouyang, C., Henson, K., Boyd, D., Callegari, S., Carter, R., Casarotto, D., Gribelyuk, M., Hargrove, M., He, W., Kim, Y., Linder, B., Moumen, N., Paruchuri, V.K., Stathis, J., Steen, M., Vayshenker, A., Wang, X., Zafar, S., Ando, T., Iijima, R., Takayanagi, M., Narayanan, V., Wise, R., Zhang, Y., Divakaruni, R., Khare, M., Chen, T.C.

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Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides by Wu, E.Y., Vayshenker, A., Nowak, E., Sune, J., Vollertsen, R.-P., Lai, W., Harmon, D.

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Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown by Wu, E.Y., Vayshenker, A., Nowak, E., Sune, J., Vollertsen, R.-P., Lai, W., Harmon, D.

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Experimental evidence of T(BD) power-law for voltage dependence of oxide breakdown in ultrathin gate oxides by Wu, E Y, Vayshenker, A, Nowak, E, Sune, J, Vollertsen, R-P, Lai, W, Harmon, D

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High performance and low power transistors integrated in 65nm bulk CMOS technology by Luo, Z., Steegen, A., Eller, M., Mann, R., Baiocco, C., Nguyen, P., Kim, L., Hoinkis, M., Ku, V., Klee, V., Jamin, F., Wrschka, P., Shafer, P., Lin, W., Fang, S., Ajmera, A., Tan, W., Park, D., Mo, R., Lian, J., Vietzke, D., Coppock, C., Vayshenker, A., Hook, T., Chan, V., Kim, K., Cowley, A., Kim, S., Kaltalioglu, E., Zhang, B., Marokkey, S., Lin, Y., Lee, K., Zhu, H., Weybright, M., Rengarajan, R., Ku, J., Schiml, T., Sudijono, J., Yang, I., Wann, C.

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Voltage-dependent voltage-acceleration of oxide breakdown for ultra-thin oxides by Wu, E.Y., Aitken, J., Nowak, E., Vayshenker, A., Varekamp, P., Hueckel, G., McKenna, J., Harmon, D., Han, L.-K., Montrose, C., Dufresne, R.

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High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology by Luo, Z., Rovedo, N., Ong, S., Phoong, B., Eller, M., Utomo, H., Ryou, C., Wang, H., Stierstorfer, R., Clevenger, L., Kim, S., Toomey, J., Sciacca, D., Li, J., Wille, W., Zhao, L., Teo, L., Dyer, T., Fang, S., Yan, J., Kwon, O., Park, D., Holt, J., Han, J., Chan, V., Yuan, J., Kebede, T., Lee, H., Kim, S., Lee, S., Vayshenker, A., Yang, Z., Tian, C., Ng, H., Shang, H., Hierlemann, M., Ku, J., Sudijono, J., Ieong, M.

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Critical reliability challenges in scaling SiO 2-based dielectric to its limit by Wu, E.Y., Suñé, J., Lai, W., Vayshenker, A., Nowak, E., Harmon, D.

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