Reliability study on cobalt and ruthenium as alternative metals for advanced interconnects by Pedreira, O. Varela, Croes, K., Lesniewska, A., Wu, C., van der Veen, M. H., de Messemaeker, J., Vandersmissen, K., Jourdan, N., Wen, L. G., Adelmann, C., Briggs, B., Gonzalez, V. Vega, Bömmels, J., Tokei, Zs

Request full text

BEOL tip-to-tip dielectric reliability characterization using a design-representative test structure by Fang, Y., Lesniewska, A., Ciofi, I., Roussel, Ph, Wu, C., Vega-Gonzalez, V., De Wolf, I., Croes, K.

Request full text

Metal reliability mechanisms in Ruthenium interconnects by Pedreira, O. Varela, Stucchi, M., Gupta, A., Gonzalez, V. Vega, van der Veen, M., Lariviere, S., Wilson, C.J., Tokei, Zs, imec, K. Croes

Request full text

Dielectric Reliability Study of 21 nm Pitch Interconnects with Barrierless Ru Fill by Lesniewska, A., Roussel, P.J., Tierno, D., Gonzalez, V. Vega, van der Veen, M. H., Verdonck, P., Jourdan, N., Wilson, C.J., Tokei, Zs, Croes, K.

Request full text

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/Low-k interconnects by Jourdan, N., van der Veen, M. H., Vega Gonzalez, V., Croes, K., Lesniewska, A., Varela Pedreira, O., Van Elshocht, S., Bommels, J., Tokei, Zs

Request full text

3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling by Horiguchi, N., Mertens, H., Chiarella, T., Demuynck, S., Vega-Gonzalez, V., Vandooren, A., Veloso, A., Bardon, M. Garcia, Sisto, G., Gupta, A., Tokei, Z., Biesemans, S., Ryckaert, J.

Request full text

Improving uniformity of 3-level High Aspect Ratio Supervias by Montero, D., Marien, P., Hermans, Y., Vega-Gonzalez, V., Feurprier, Y., Oikawa, N., Buccheri, N., Wu, C., Martinez, G.T., Batuk, D., Puliyalil, H., Decoster, S., Kumar, K., Lazzarino, F., Murdoch, G., Park, S., Tokei, Z.

Request full text

Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below by Montero, D., Vega-Gonzalez, V., Feurprier, Y., Pedreira, O. Varela, Oikawa, N., Martinez, G.T., Batuk, D., Puliyalil, H., Versluijs, J., Decoster, H., Bazzazian, N., Jourdan, N., Kumar, K., Lazzarino, F., Murdoch, G., Park, S., Tokei, Z.

Request full text

Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells by Vega-Gonzalez, V., Radisic, D., Choudhury, S., Tierno, D., Thiam, A., Batuk, D., Martinez, G.T., Seidel, F., Decoster, S., Kundu, S., Tsvetanova, D., Peter, A., De Coster, H., Sepulveda-Marquez, A., Altamirano-Sanchez, E., Chan, Bt, Drissi, Y., Sherazi, Y., Uk-Lee, J., Ciofi, I., Murdoch, G., Nagesh, N., Hellings, G., Ryckaert, J., Biesemans, S., Litta, E. Dentoni, Horiguchi, N., Park, S., Tokei, Zs

Request full text

Hybrid Metallization with Cu in sub 30nm Interconnects by van der Veen, Marleen H., Soethoudt, J., Delabie, A., Pedreira, O. Varela, Vega Gonzalez, V., Lariviere, S., Teugels, L., Jourdan, N., Decoster, S., Struyf, H., Wilson, C. J., Croes, K., Tokei, Zs

Request full text

Electromigration and Thermal Storage Study of Barrierless Co Vias by Pedreira, O. Varela, Croes, K., Zahedmanesh, H., Vandersmissen, K., van der Veen, M. H., Gonzalez, V. Vega, Dictus, D., Zhao, L., Kolies, A., Tokei, Zs

Request full text

Development of a Cu and W Compatible PERR Clean in BEOL Advanced Interconnect Patterning by Kesters, Els, Le, Quoc Toan, Decoster, Stefan, Vega Gonzalez, Victor, Holsteyns, Frank, De Gendt, Stefan

Get full text

Barrier/liner stacks for scaling the Cu interconnect metallization by van der Veen, Marleen H., Jourdan, N., Gonzalez, V. Vega, Wilson, C. J., Heylen, N., Pedreira, O. Varela, Struyf, H., Croes, K., Bommels, J., Tokei, Zs

Request full text

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts by Demuynck, S., Gonzalez, V. Vega, de Carvalho Cavalcante, C. Toledo, Lima, L.P.B., Stiers, K., Sheng, C., Vandooren, A., Hosseini, M., Zhou, X., Mertens, H., Chiarella, T., Bommels, J., Loo, R., Rosseel, E., Porret, C., Shimura, Y., Akula, A., Mannaert, G., Choudhury, S., Brissonneau, V., Dupuy, E., Sarkar, T., Vergel, N. Franchina, Peter, A., Jourdan, N., Soulie, J.P., Vandersmissen, K., Sebaai, F., Gowda, P. Puttarame, Lai, K., Mingardi, A., Sarkar, S. Sumar, Dhave, K., Chan, B. T., Marquez, A. Sepulveda, Langer, R., Koo, I. Gyo, Sanchez, E. Altamirano, Devriendt, K., Delgadillo, P. Rincon, Lazzarino, F., Mitard, J., Geypen, J., Grieten, E., Batuk, D., Chen, Y-F., Verbeek, F., Holsteyns, F., Subramanian, S., Horiguchi, N., Biesemans, S.

Request full text

Semi-empirical interconnect resistance model for advanced technology nodes: A model apt for materials selection based upon test line resistance measurements by Roussel, Ph J., Ciofi, I., Degraeve, R., Gonzalez, V. Vega, Jourdan, N., Baert, R., Linten, D., Bommels, J., Tokei, Z., Groeseneken, G., Thean, A.

Request full text

Integration of Al2O3 Etch Stop Layer in 21nm Pitch Dual-Damascene BEOL interconnects by Wu, C., Vega-Gonzalez, V., De Coster, H., Le, Q. T., Schleicher, F., Lesniewska, A., Murdoch, G., Park, S., Tokei, Zs

Request full text

Front-side Integration of Middle-of-line Stacked Contacts for Monolithic CFET by Vega-Gonzalez, V., Stiers, K., Sheng, C., Demuynck, S., de Carvalho Cavalcante, C Toledo, Petersen, L., Chiarella, T., Boemmels, J., Sarkar, T., Vergel, N. Franchina, Radisic, D., Loo, R., Rosseel, E., Porret, C., Mannaert, G., Choudhury, S., Brissonneau, V., Dupuy, E., Peter, A., Jourdan, N., Soulie, J-P., Hakamata, T., Romo-Negreira, A., Clark, R., Vandersmissen, K., Sebaai, F., Gowda, P. Puttarame, Lai, J.G., Mingardi, A., Sarkar, S. Kumar, Chan, B. T., Marquez, A. Sepulveda, Langer, R., Koo, I. Gyo, Sanchez, E. Altamirano, Devriendt, K., Delgadillo, P. Rincon, Lazzarino, F., Mitard, J., Geypen, J., Batuk, D., Chen, Y-F., Verbeeck, F., Holsteyns, F., Subramanian, S., Tokei, Zs, Horiguchi, N., Biesemans, S.

Request full text

Damascene Benchmark of Ru, Co and Cu in Scaled Dimensions by van der Veen, Marleen H., Heyler, N., Pedreira, O. Varela, Ciofi, I., Decoster, S., Gonzalez, V. Vega, Jourdan, N., Struyf, H., Croes, K., Wilson, C. J., Tokei, Zs

Request full text

Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node by Vega-Gonzalez, V., Bekaert, J., Kesters, E., Le, Q. T., Lorant, C., Varela P., O., Teugels, L., Heylen, N., El-Mekki, Z., van der Veen, M., Webers, T., Wilson, C. J., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Briggs, B., Kimura, Y., Jourdan, N., Ciofi, I., Gupta, A., Contino, A., Boccardi, G., Lariviere, S., Dupas, L., De-Wachter, B., Vancoille, E., Decoster, S., Lazzarino, F., Ercken, M, Debacker, P., Kim, R., Trivkovic, D., Croes, K., Leray, P., Dillemans, L., Chen, Y.-F., Tokei, Z., Versluijs, J., Lesniewska, A., Paolillo, S., Baert, R., Puliyalil, H.

Request full text

Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations by Vega-Gonzalez, V., Montero, D., Versluijs, J., Pedreira, O. Varela, Jourdan, N., Puliyalil, H., Chehab, B., Peissker, T., Haider, A., Batuk, D., Martinez, G. T., Geypen, J., Le, Q. T., Bazzazian, N., Heylen, N., van der Veen, M., El-Mekki, Z., Webers, T., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Gillijns, W., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Kimura, Y., Ciofi, I., De Wachter, B., Swerts, J., Grieten, E., Ercken, M., Kim, R., Croes, K., Leray, P., Jaysankar, M., Nagesh, N., Ramakers, L., Murdoch, G., Park, S., Tokei, Z., Dentoni-Litta, E., Horiguchi, N.

Request full text