Search Results - Vestias, M.

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  1. 1
    MULTI-GNSS RECEIVER FOR AEROSPACE NAVIGATION AND POSITIONING APPLICATIONS

    MULTI-GNSS RECEIVER FOR AEROSPACE NAVIGATION AND POSITIONING APPLICATIONS by Peres, T. R., Silva, J. S., Silva, P. F., Carona, D., Serrador, A., Palhinha, F., Pereira, R., Véstias, M.

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  2. 2
    FPGA implementation of IEEE 802.15.3c receiver

    FPGA implementation of IEEE 802.15.3c receiver by Vestias, M., Sarmento, H.

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  3. 3
    DCM demapper for MB-OFDM on FPGA

    DCM demapper for MB-OFDM on FPGA by Vestias, M., Santos, H., Sarmento, H.

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  4. 4
    Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA

    Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA by Vestias, M.

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  5. 5
    A High-Rate MIMO Receiver in an FPGA

    A High-Rate MIMO Receiver in an FPGA by Pinho, Pedro, Vestias, M.

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  6. 6
    Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm

    Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm by Vestias, M., Neto, H.

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  7. 7
    Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs

    Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs by Duarte, R., Neto, H., Vestias, M.

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  8. 8
    Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems

    Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems by Vestias, M., Sarmento, H.

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  9. 9
    Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions

    Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions by Silva, V., Vestias, M. P., Neto, H. C., Fernandes, J. R.

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  10. 10
    Design of an IEEE 802.15.3c baseband processor in FPGA

    Design of an IEEE 802.15.3c baseband processor in FPGA by Vestias, M., Sarmento, H.

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  11. 11
    Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

    Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs by Vestias, M., Neto, H., Sarmento, H.

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  12. 12
    System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures

    System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures by Vestias, M.P., Neto, H.C.

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  13. 13
    DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]

    DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example] by Vestias, M.P., Neto, H.C.

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  14. 14
    A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory

    A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory by Silva, V., Fernandes, J. R., Vestias, M. P., Neto, H. C.

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  15. 15
    Design of a massively parallel computing architecture for dense matrix multiplication

    Design of a massively parallel computing architecture for dense matrix multiplication by Jose, W., Silva, A. R., Vestias, M., Neto, H.

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  16. 16
    Iterative decimal multiplication using binary arithmetic

    Iterative decimal multiplication using binary arithmetic by Vestias, M P, Neto, H C

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  17. 17
    Design of a multiband full-rate ultra-wideband receiver in FPGA

    Design of a multiband full-rate ultra-wideband receiver in FPGA by Vestias, M., Neto, H., Sarmento, H.

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  18. 18
    Revisiting the Newton-Raphson Iterative Method for Decimal Division

    Revisiting the Newton-Raphson Iterative Method for Decimal Division by Vestias, M. P., Neto, H. C.

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  19. 19
    Sliding block Viterbi decoders in FPGA

    Sliding block Viterbi decoders in FPGA by Vestias, M., Neto, H., Sarmento, H.

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  20. 20
    A dynamic buffer resize technique for networks-on-chip on FPGA

    A dynamic buffer resize technique for networks-on-chip on FPGA by Vestias, M P, Neto, H C

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