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A self-duty-cycled and synchronized UWB receiver SoC consuming 375pJ/b for −76.5dBm sensitivity at 2Mb/s
by
Vigraham, B.
,
Kinget, P.
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A 16 MHz BW 75 dB DR CT \Delta\Sigma ADC Compensated for More Than One Cycle Excess Loop Delay
by
Singh, V.
,
Krishnapura, N.
,
Pavan, S.
,
Vigraham, B.
,
Behera, D.
,
Nigania, N.
Published in
IEEE journal of solid-state circuits
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An ultra low power, compact UWB receiver with automatic threshold recovery in 65 nm CMOS
by
Vigraham, B.
,
Kinget, P. R.
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A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay
by
Singh, V.
,
Krishnapura, N.
,
Pavan, S.
,
Vigraham, B.
,
Nigania, N.
,
Behera, D.
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Ieee Journal Of Solid-State Circuits
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Delay
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Demodulation
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Feedforward Neural Networks
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