Search Results - Vrigno, B.

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    CESAME: a test chip for the validation of a parasitic emission prediction flow in 0.18 /spl mu/m CMOS technology

    CESAME: a test chip for the validation of a parasitic emission prediction flow in 0.18 /spl mu/m CMOS technology by Vrigno, B., Bendhia, S., Courau, L., Sicard, E.

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    CESAME : A test chip for the validation of a parasitic emission prediction flow in 0.18μm CMOS technology

    CESAME : A test chip for the validation of a parasitic emission prediction flow in 0.18μm CMOS technology by VRIGNO, Bertrand, BENDHIA, S, COURAU, L, SICARD, E

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