Search Results - Vrudhula, Sarma B.K.

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  1. 1
    A methodology to improve timing yield in the presence of process variations

    A methodology to improve timing yield in the presence of process variations by Raj, Sreeja, Vrudhula, Sarma B. K., Wang, Janet

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  2. 2
    Estimation of the likelihood of capacitive coupling noise

    Estimation of the likelihood of capacitive coupling noise by Vrudhula, S.B.K., Blaauw, D., Sirichotiyakul, S.

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  3. 3
    Programmable Analog/Digital Arrays in Control and Simulation

    Programmable Analog/Digital Arrays in Control and Simulation by Znamirowski, Lech, Palusinski, Olgierd A., Vrudhula, Sarma B.K.

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  4. 4
    Implicit pseudo boolean enumeration algorithms for input vector control

    Implicit pseudo boolean enumeration algorithms for input vector control by Chopra, Kaviraj, Vrudhula, Sarma B. K.

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  5. 5
    Behavioral synthesis of field programmable analog array circuits

    Behavioral synthesis of field programmable analog array circuits by Wang, Haibo, Vrudhula, Sarma B. K.

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  6. 6
    EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition

    EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition by Lai, Y.-T., Pedram, M., Vrudhula, S.B.K.

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  7. 7
    Formal verification using edge-valued binary decision diagrams

    Formal verification using edge-valued binary decision diagrams by Yung-Te Lai, Pedram, M., Vrudhula, S.B.K.

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  8. 8
    Fault coverage and test length estimation for random pattern testing

    Fault coverage and test length estimation for random pattern testing by Majumdar, A., Vrudhula, S.B.K.

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  9. 9
    Investigation of power delay trade-offs on powerPC circuits

    Investigation of power delay trade-offs on powerPC circuits by Wang, Qi, Vrudhula, Sarma B K, Ganguly, Shantanu

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  10. 10
    A design of a fast and area efficient multi-input Muller C-element

    A design of a fast and area efficient multi-input Muller C-element by Wuu, T.-Y., Vrudhula, S.B.K.

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  11. 11
    BDD based decomposition of logic functions with application to FPGA synthesis

    BDD based decomposition of logic functions with application to FPGA synthesis by Lai, Yung-Te, Pedram, Massoud, Vrudhula, Sarma B. K.

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  12. 12
    Data driven power optimization of sequential circuits

    Data driven power optimization of sequential circuits by Qi Wang, Vrudhula, S.B.K.

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  13. 13
    Estimation of signal arrival times in the presence of delay noise

    Estimation of signal arrival times in the presence of delay noise by BHARDWAJ, Sarvesh, VRUDHULA, Sarma B. K, BLAAUW, David

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  14. 14
    Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts

    Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts by Ho, K.C., Vrudhula, S.B.K.

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  15. 15
    Techniques for estimating test length under random test

    Techniques for estimating test length under random test by Majumdar, Amitava, Vrudhula, Sarma B. K.

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  16. 16
    Automatic design of binary and multiple-valued logic gates on RTD series

    Automatic design of binary and multiple-valued logic gates on RTD series by Berezowski, K.S., Vrudhula, S.B.K.

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  17. 17
    Hardware-software bipartitioning for dynamically reconfigurable systems

    Hardware-software bipartitioning for dynamically reconfigurable systems by Rakhmatov, Daler N., Vrudhula, Sarma B. K.

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  18. 18
    A new short circuit power model for complex CMOS gates

    A new short circuit power model for complex CMOS gates by Wang, Q., Vrudhula, S.B.K.

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  19. 19
    Rapid prototyping of networks of asynchronous multiple functional units

    Rapid prototyping of networks of asynchronous multiple functional units by Tsun, E., Vrudhula, S.B.K.

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  20. 20
    Macro-instruction generation for dynamic logic caching

    Macro-instruction generation for dynamic logic caching by McCarley, K., Vrudhula, S.B.K.

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