Analysis and Mitigation of Parasitic Mode Conversion for Microstrip to Stripline Transitions by Rimolo-Donadio, Renato, Supper, J., Winkel, T., Harrer, H., Schuster, C.

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Application of the Short-Pulse Propagation Technique for Broadband Characterization of PCB and Other Interconnect Technologies by Deutsch, Alina, Krabbenhoft, Roger S, Melde, Kathleen L, Surovic, Christopher W, Katopis, George A, Kopcsay, Gerard V, Zhen Zhou, Zhaoqing Chen, Kwark, Young H, Winkel, Thomas-Michael, Xiaoxiong Gu, Standaert, Theodorus E

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Signal via coupling effects caused by partially broken high frequency signal return by Winkel, Thomas-Michael

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The IEEE EPS Packaging Benchmark Suite by Guo, Fei, Aygun, Kemal, Becker, W. Dale, Talocia, Stefano Grivet, Hejase, Jose A., Wong, Wui-Weng, Zhou, Tingdong, Barnes, Heidi, Peng, Zhen, Pelger, Alexander, Sahouli, Mohamed, Schutt-Aine, Jose, Ling, Feng, Griese, Elmar, Paladhi, Pavel Roy, Sharma, Rohit, Pham, Nam, Winkel, Thomas-Michael, Fledell, Evan, Hill, Michael J., Silva, Benjamin, Hu, Kaisheng, Aronsson, Jonatan, Liu, Chang, Jeong, Yiru, Yilmaz, Ali E.

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Framework for co-simulation of signal and power integrity in server systems by Winkel, T., Harrer, H., Strach, T., Rimolo-Donadio, Renato, Kwark, Y., Xiaomin Duan, Schuster, C.

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Long Range Connector Via Coupling Effects for High Speed Signals by Winkel, Thomas-Michael, Frech, Roland, Gneiting, Thomas

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Fast parametric pre-layout analysis of signal integrity for backplane interconnects by Rimolo-Donadio, Renato, Winkel, T., Siviero, C., Kaller, D., Harrer, H., Bruns, H., Schuster, C.

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Extraction of εr(f) and tan δ(f) for printed circuit board insulators up to 30 GHz using the short-pulse propagation technique by DEUTSCH, Alina, WINKEL, Thomas-Michael, KOPCSAY, Gerard V, SUROVIC, Christopher W, RUBIN, Barry J, KATOPIS, George A, CHAMBERLIN, Bruce J, KRABBENHOFT, Roger S

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Impact of Broken High Frequency Signal Return Path on Signal Integrity by Winkel, T.-M., Frech, R., Klink, E., Kaller, D., Genovese, E.

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Packaging design challenges of the IBM System z10 Enterprise Class server by Winkel, T-M, Harrer, H, Kaller, D, Supper, J, Dreps, D M, Christian, K L, Cosmadelis, D, Zhou, T, Strach, T, Ludwig, J, Edwards, D L

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High-speed interconnect and packaging design of the IBM System z9 processor cage by Harrer, H., Dreps, D. M., Winkel, T.-M., Scholz, W., Truong, B. G., Huber, A., Zhou, T., Christian, K. L., Goth, G. F.

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Determination of transmission line parameters in time- and frequency domain for product related packaging structures by Winkel, T.-M., Deutsch, A., Katopis, G.A., Kopcsay, G.V., Dyckman, W.D., Chamberlin, B., Surovic, C.W., Liu, H., Baks, C.

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First- and second-level packaging of the z990 processor cage by Winkel, T.-M., Becker, W. D., Harrer, H., Pross, H., Kaller, D., Garben, B., Chamberlin, B. J., Kuppinger, S. A.

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First- and second-level packaging for the IBM eServer z900 by Harrer, H., Pross, H., Winkel, T.-M., Becker, W. D., Stoller, H. I., Yamamoto, M., Abe, S., Chamberlin, B. J., Katopis, G. A.

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Methods for calculation of eye diagrams for digital links with multiple aggressors having unknown time offsets by Timmermann, D., Rimolo-Donadio, Renato, Kwark, Y. H., Winkel, T-M, Siviero, C., Harrer, H., Schuster, C.

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An accurate determination of the characteristic impedance matrix of coupled symmetrical lines on chips based on high frequency S-parameter measurements by Winkel, T.-M., Dutta, L.S., Grabinski, H.

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Effects of partially broken HF signal return on different packaging levels by Winkel, T.-M., Frech, R., Gneiting, T.

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Crosstalk analysis in high density connector via pin fields for digital backplane applications using a 12-port vector network analyzer by Kotzev, M, Frech, R, Harrer, H, Kaller, D, Huber, A, Winkel, T.-M, Brüns, H.-D, Schuster, C

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Comparison of time- and frequency domain measurement results for product related card and MCM transmission lines up to 65 GHz by Winkel, T.-M., Deutsch, A., Katopis, G.A., Kopcsay, G.V., Klink, E., Dyckman, W.D., Chamberlin, B.J., Grabinski, H., Surovic, C.W., Liu, H., Baks, C.

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Efficient modeling methodology and hardware validation of glass-ceramic based wiring for high-performance single- and multi-chip modules by Sungjun Chun, Haridass, A., Deutsch, A., Rubin, B., Surovic, C., Klink, E., O'Connor, D., Hsichang Liu, Spring, C., Winkel, T.-M., Dyckman, W., Katopis, G., Kopcsay, G.

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