Search Results - Waicukauski, John A.

Refine Results
  1. 1
    Fully X-tolerant, very high scan compression

    Fully X-tolerant, very high scan compression by Wohl, Peter, Waicukauski, John A, Neuveux, Frederic, Gizdarski, Emil

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  2. 2
    Effective diagnostics through interval unloads in a BIST environment

    Effective diagnostics through interval unloads in a BIST environment by Wohl, Peter, Waicukauski, John A., Patel, Sanjay, Maston, Greg

    Get full text
    Conference Proceeding
    Save to List
    Saved in:
  3. 3
    Scalable selector architecture for x-tolerant deterministic BIST

    Scalable selector architecture for x-tolerant deterministic BIST by Wohl, Peter, Waicukauski, John A., Patel, Sanjay

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  4. 4
    Achieving extreme scan compression for SoC Designs

    Achieving extreme scan compression for SoC Designs by Wohl, Peter, Waicukauski, John A., Colburn, Jonathon E., Sonawane, Milind

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  5. 5
    X-tolerant compression and application of scan-atpg patterns in a bist architecture

    X-tolerant compression and application of scan-atpg patterns in a bist architecture by Wohl, P., Waicukauski, J.A., Patel, S., Amin, M.B.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  6. 6
    Efficient compression of deterministic patterns into multiple PRPG seeds

    Efficient compression of deterministic patterns into multiple PRPG seeds by Wohl, P., Waicukauski, J.A., Patel, S., DaSilva, F., Williams, T.W., Kapur, R.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  7. 7
    Design of compactors for signature-analyzers in built-in self-test

    Design of compactors for signature-analyzers in built-in self-test by Wohl, P., Waicukauski, J.A., Williams, T.W.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  8. 8
    Automated Design and Insertion of Optimal One-Hot Bus Encoders

    Automated Design and Insertion of Optimal One-Hot Bus Encoders by Wohl, P., Waicukauski, J.A., Patel, S.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  9. 9
    Hierarchical compactor design for diagnosis in deterministic logic BIST

    Hierarchical compactor design for diagnosis in deterministic logic BIST by Wohl, P., Waicukauski, J.A., Patel, S., Hay, C., Gizdarski, E., Mathew, B.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  10. 10
    On computing the sizes of detected delay faults

    On computing the sizes of detected delay faults by Iyengar, V.S., Rosen, B.K., Waicukauski, J.A.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  11. 11
    A method for generating weighted random test patterns

    A method for generating weighted random test patterns by WAICUKAUSKI, J. A, LINDBLOOM, E, EICHELBERGER, E. B, FORLENZA, O. P

    Get full text
    Items that cite this one
    Article
    Save to List
    Saved in:
  12. 12
    Failure diagnosis of structured VLSI

    Failure diagnosis of structured VLSI by Waicukauski, J.A., Lindbloom, E.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  13. 13
    Transition Fault Simulation

    Transition Fault Simulation by Waicukauski, John A., Lindbloom, Eric, Rosen, Barry K., Iyengar, Vijay S.

    Get full text
    Items that this one cites
    Items that cite this one
    Article
    Save to List
    Saved in:
  14. 14
    Scan test data volume reduction in multi-clocked designs with safe capture technique

    Scan test data volume reduction in multi-clocked designs with safe capture technique by Jain, V., Waicukauski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  15. 15
    Optimizing the flattened test-generation model for very large designs

    Optimizing the flattened test-generation model for very large designs by Wohl, P., Waicukauski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  16. 16
    Using Verilog simulation libraries for ATPG

    Using Verilog simulation libraries for ATPG by Wohl, P., Waicukauski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  17. 17
    Defining ATPG rules checking in STIL

    Defining ATPG rules checking in STIL by Wohl, P., Waicukauski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  18. 18
    Test generation for ultra-large circuits using ATPG constraints and test-pattern templates

    Test generation for ultra-large circuits using ATPG constraints and test-pattern templates by Wohl, P., Waicukauski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  19. 19
    A unified interface for scan test generation based on STIL

    A unified interface for scan test generation based on STIL by Wohl, P., Waicukauski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:
  20. 20
    Extracting gate-level networks from simulation tables

    Extracting gate-level networks from simulation tables by Wohl, P., Waicukanski, J.

    Request full text
    Conference Proceeding
    Save to List
    Saved in:

Search Tools: