Search Results - Wajsburt, F.

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  1. 1
    An out-of-order superscalar processor on FPGA: The ReOrder Buffer design

    An out-of-order superscalar processor on FPGA: The ReOrder Buffer design by Rosiere, M., Desbarbieux, J.-I, Drach, N., Wajsburt, F.

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  2. 2
    On the scalability of image and signal processing parallel applications on emerging cc-NUMA many-cores

    On the scalability of image and signal processing parallel applications on emerging cc-NUMA many-cores by Almaless, G., Wajsburt, F.

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  3. 3
    Transistor controlled slew rate process independent PCI compliant I/O buffer with possible power/delay trade-off

    Transistor controlled slew rate process independent PCI compliant I/O buffer with possible power/delay trade-off by Wajsbürt, F., Pétrot, F., Dioury, K.

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  4. 4
    Programmable routers for efficient mapping of applications onto NoC-based MPSoCs

    Programmable routers for efficient mapping of applications onto NoC-based MPSoCs by Djemal, M., Pecheux, F., Potop-Butucaru, D., de Simone, R., Wajsburt, F., Zhen Zhang

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  5. 5
    Morpheo: A high-performance processor generator for a FPGA implementation

    Morpheo: A high-performance processor generator for a FPGA implementation by Rosiere, M., Desbarbieux, Jean-Lou, Drach, N., Wajsburt, F.

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  6. 6
    Low power, process independent, full transistor controlled slew rate, PCI compliant I/O pads

    Low power, process independent, full transistor controlled slew rate, PCI compliant I/O pads by Wajsburt, F., Dioury, K., Petrot, F.

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  7. 7
    Designing a high complexity microprocessor using the Alliance CAD system

    Designing a high complexity microprocessor using the Alliance CAD system by Greiner, A., Lucas, L., Wajsburt, F.

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  8. 8
    High level synthesis methodology from C to FPGA used for a network protocol communication

    High level synthesis methodology from C to FPGA used for a network protocol communication by Diaby, M., Tuna, M., Desbarbieux, J.L., Wajsburt, F.

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  9. 9
    Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

    Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library by Greiner, A., Lucas, L., Wajsburt, F., Winckel, L.

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  10. 10
    Protocol and performance analysis of the MPC parallel computer

    Protocol and performance analysis of the MPC parallel computer by Gluck, O., Zerrouki, A., Desbarbieux, J.L., Fenyo, A., Grener, A., Wajsburt, F., Spasevski, C., Silva, F., Dreyfus, E.

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  11. 11
    Implementation of Complex Strategies of Security Insecure Embedded Systems

    Implementation of Complex Strategies of Security Insecure Embedded Systems by Robisson, B, Agoyan, M, Le Henaff, S, Soquet, P, Phan, G, Wajsbürt, F, Bazargan-Sabet, P

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