Search Results - Wilke, Gustavo

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  1. 1
    Revisiting automated physical synthesis of high-performance clock networks

    Revisiting automated physical synthesis of high-performance clock networks by Guthaus, Matthew R., Wilke, Gustavo, Reis, Ricardo

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  2. 2
    High-performance clock mesh optimization

    High-performance clock mesh optimization by Guthaus, Matthew, Hu, Xuchu, Wilke, Gustavo, Flach, Guilherme, Reis, Ricardo

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  3. 3
    Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface

    Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface by Cheng Zhuo, Wilke, Gustavo, Chakraborty, Ritochit, Aydiner, Alaeddin A., Chakravarty, Sourav, Wei-Kai Shih

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  4. 4
    Gate sizing using geometric programming

    Gate sizing using geometric programming by Posser, Gracieli, Flach, Guilherme, Wilke, Gustavo, Reis, Ricardo

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  5. 5
    Non-uniform clock mesh optimization with linear programming buffer insertion

    Non-uniform clock mesh optimization with linear programming buffer insertion by Guthaus, Matthew R, Wilke, Gustavo, Reis, Ricardo

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  6. 6
    A silicon-validated methodology for power delivery modeling and simulation

    A silicon-validated methodology for power delivery modeling and simulation by Zhuo, Cheng, Wilke, Gustavo, Chakraborty, Ritochit, Aydiner, Alaeddin, Chakravarty, Sourav, Shih, Wei-Kai

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  7. 7
    A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction

    A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction by Wilke, G., Reis, R.

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  8. 8
    Analyzing Timing Uncertainty in Mesh-based Clock Architectures

    Analyzing Timing Uncertainty in Mesh-based Clock Architectures by Reddy, S.M., Wilke, G.R., Rajeev Murgai

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  9. 9
    Variability-aware physical design techniques

    Variability-aware physical design techniques by Wilke, Gustavo, Reis, Ricardo

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  10. 10
    Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme

    Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme by Santos, C., Ferrao, D., Lazzari, C., Wilke, G., Guntzel, J.L., Reis, R.

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  11. 11
    A study on layout quality of automatic generated cells

    A study on layout quality of automatic generated cells by Posser, Gracieli, Ziesemer, Adriel, Guimares, Daniel, Wilke, Gustavo, Reis, Ricardo

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  12. 12
    Gate Sizing Minimizing Delay and Area

    Gate Sizing Minimizing Delay and Area by Posser, G., Flach, G., Wilke, G., Reis, R.

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  13. 13
    Transistor sizing and gate sizing using geometric programming considering delay minimization

    Transistor sizing and gate sizing using geometric programming considering delay minimization by Posser, Gracieli, Flach, G., Wilke, G., Reis, R.

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  14. 14
    Tradeoff between delay and area in gate sizing using Geometric Programming

    Tradeoff between delay and area in gate sizing using Geometric Programming by Posser, G., Flach, G., Wilke, G., Reis, R.

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  15. 15
    A Mesh-Buffer Displacement Optimization Strategy

    A Mesh-Buffer Displacement Optimization Strategy by Flach, Guilherme, Wilke, Gustavo, Johann, Marcelo, Reis, Ricardo

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  16. 16
    Gate sizing using Geometric Programming

    Gate sizing using Geometric Programming by Posser, G, Flach, G, Wilke, G, Reis, R

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  17. 17
    A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits

    A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits by Sawicki, S., Wilke, G., Johann, M., Reis, R.

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  18. 18
    Design and Analysis of "Tree+Local Meshes" Clock Architecture

    Design and Analysis of "Tree+Local Meshes" Clock Architecture by Wilke, G.R., Murgai, R.

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  19. 19
    Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times

    Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times by Ferrao, D., Wilke, G., Reis, R., Neves, C., Agostini, L., Guntzel, J.

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  20. 20
    A Transistor Sizing Method Applied to an Automatic Layout Generation Tool

    A Transistor Sizing Method Applied to an Automatic Layout Generation Tool by Santos, Cristiano, Wilke, Gustavo, Lazzari, Cristiano, Reis, Ricardo, Güntzel, José Luís

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