Search Results - Wistoff, Nils

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  1. 1
    Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

    Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning by Wistoff, Nils, Schneider, Moritz, Gurkaynak, Frank K., Heiser, Gernot, Benini, Luca

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  2. 2
    A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation

    A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation by Valente, Luca, Nadalini, Alessandro, Veeran, Asif Hussain Chiralil, Sinigaglia, Mattia, Sa, Bruno, Wistoff, Nils, Tortorella, Yvan, Benatti, Simone, Psiakis, Rafail, Kulmala, Ari, Mohammad, Baker, Pinto, Sandro, Palossi, Daniele, Benini, Luca, Rossi, Davide

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  3. 3
    Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

    Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core by Wistoff, Nils, Schneider, Moritz, Gurkaynak, Frank K., Benini, Luca, Heiser, Gernot

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  4. 4
    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Float... by Paulin, Gianna, Scheffler, Paul, Benz, Thomas, Cavalcante, Matheus, Fischer, Tim, Eggimann, Manuel, Zhang, Yichao, Wistoff, Nils, Bertaccini, Luca, Colagrande, Luca, Ottavi, Gianmarco, Gurkaynak, Frank K., Rossi, Davide, Benini, Luca

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  5. 5
    A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design

    A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design by Perotti, Matteo, Cavalcante, Matheus, Wistoff, Nils, Andri, Renzo, Cavigelli, Lukas, Benini, Luca

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  6. 6
    On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

    On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster by Rogenmoser, Michael, Wistoff, Nils, Vogel, Pirmin, Gürkaynak, Frank, Benini, Luca

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  7. 7
    On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

    On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster by Rogenmoser, Michael, Wistoff, Nils, Vogel, Pirmin, Gurkaynak, Frank, Benini, Luca

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  8. 8
    fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning

    fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning by Wistoff, Nils, Heiser, Gernot, Benini, Luca

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  9. 9
    A ''New Ara'' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design

    A ''New Ara'' for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design by Perotti, Matteo, Cavalcante, Matheus, Wistoff, Nils, Andri, Renzo, Cavigelli, Lukas, Benini, Luca

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  10. 10
    Towards a RISC-V Open Platform for Next-generation Automotive ECUs

    Towards a RISC-V Open Platform for Next-generation Automotive ECUs by Cuomo, Luca, Scordino, Claudio, Ottaviano, Alessandro, Wistoff, Nils, Balas, Robert, Benini, Luca, Errico Guidieri, Savino, Ida Maria

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  11. 11
    A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation

    A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation by Valente, Luca, Nadalini, Alessandro, Veeran, Asif, Sinigaglia, Mattia, Sa, Bruno, Wistoff, Nils, Tortorella, Yvan, Benatti, Simone, Psiakis, Rafail, Kulmala, Ari, Baker, Mohammad, Pinto, Sandro, Palossi, Daniele, Benini, Luca, Rossi, Davide

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  12. 12
    vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems

    vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems by Zelioli, Enrico, Ottaviano, Alessandro, Balas, Robert, Wistoff, Nils, Garofalo, Angelo, Benini, Luca

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  13. 13
    Proving the Absence of Microarchitectural Timing Channels

    Proving the Absence of Microarchitectural Timing Channels by Buckley, Scott, Sison, Robert, Wistoff, Nils, Millar, Curtis, Murray, Toby, Klein, Gerwin, Heiser, Gernot

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  14. 14
    Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor

    Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor by Tedeschi, Riccardo, Valente, Luca, Ottavi, Gianmarco, Zelioli, Enrico, Wistoff, Nils, Giacometti, Massimiliano, Abdul Basit Sajjad, Benini, Luca, Rossi, Davide

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  15. 15
    Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

    Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning by Wistoff, Nils, Schneider, Moritz, Gürkaynak, Frank K, Heiser, Gernot, Benini, Luca

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  16. 16
    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Float... by Paulin, Gianna, Scheffler, Paul, Benz, Thomas, Cavalcante, Matheus, Fischer, Tim, Eggimann, Manuel, Zhang, Yichao, Wistoff, Nils, Bertaccini, Luca, Colagrande, Luca, Ottavi, Gianmarco, Gürkaynak, Frank K, Rossi, Davide, Benini, Luca

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  17. 17
    Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core

    Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core by Wistoff, Nils, Schneider, Moritz, Gürkaynak, Frank K, Benini, Luca, Heiser, Gernot

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