A consideration of the design of a medical device operation support system using smart glasses by NAKATAKE, Misato, KIMURA, Tatsuhiro, SATOU, Miu, OGA, Ryo, KOSE, Ayane, YAHARA, Mitsutoshi, DOI, Kazuto

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A dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection by Fujimoto, Kuniaki, Sasaki, Hirofumi, Yahara, Mitsutoshi

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Multiple‐frequency digital phase‐locked loop based on multiphase clock divider with constant pulse interval by Yahara, Mitsutoshi, Fujimoto, Kuniaki, Kiyota, Hideo

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A Programmable Divider with 50% Duty Cycle Unrelated to Dividing Cycle and Its Application to PLL by HARADA, YUJIRO, YAHARA, MITSUTOSHI, MATSUMOTO, KINYA, FUJIMOTO, KUNIAKI

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A dividing ratio changeable digital PLL with low jitter using a multiphase clock divider by Fujimoto, Kuniaki, Yahara, Mitsutoshi, Sasaki, Hirofumi

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All digital dividing ratio changeable type phase-locked loop with a wide lock-in range by Yahara, Mitsutoshi, Sasaki, Hirotoshi, Fujimoto, Kuniaki, Sasaki, Hirofumi

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A proposition on a locked-loop based SC astable multivibrator by Sasaki, Hirofumi, Yahara, Mitsutoshi, Fujimoto, Kuniaki

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A Dividing Ratio Changeable Digital PLL Using VCO as Base Clock Source by Yahara, M., Fujimoto, K., Hirose, T., Sasaki, H.

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A new DCPLL with low jitter based on double-edge mode by Sasaki, H., Fujimoto, K., Yahara, M.

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