Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic by Yelamarthi, K., Chen, C.-I.H.

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An optimization framework for dynamic pipeline management in computing systems by Naqvi, Syed Rameez, Zahid, Anjum, Sawalha, Lina, Naqvi, Syed Saud, Akram, Tallha, Haider, Sajjad Ali, Yelamarthi, Kumar, Jenihhin, Maksim

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RFID and GPS integrated navigation system for the visually impaired by Yelamarthi, K, Haas, D, Nielsen, D, Mothersell, S

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Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations by Yelamarthi, K., Chen, Chien-In Henry

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An RFID based autonomous indoor tour guide robot by Yelamarthi, K., Sherbrook, S., Beckwith, J., Williams, M., Lefief, R.

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A Path Oriented In Time optimization flow for mixed-static-dynamic CMOS logic by Yelamarthi, K., Chen, C.-I.H.

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A timing optimization technique for nanoscale CMOS circuits susceptible to process variations by Yelamarthi, K., Chen, Chien-In Henry

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Delay optimization considering power saving in dynamic CMOS circuits by Yelamarthi, K, Chen, Chien-In Henry

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Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic by Yelamarthi, K., Chien-In Henry Chen

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Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization by Yelamarthi, K., Chen, C.-I.H.

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Low-Cost Low-Power Self-Test Design and Verification of On-Chip ADC for System-on-a-Chip Applications by Chandrasekhar, V., Chen, C.-I.H., Yelamarthi, K.

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Ultra‐Fine Aluminium Characterization and its Agglomeration Features in Solid Propellant Combustion for Various Quenched Distance and Pressure by Tejasvi, K., Venkateshwara Rao, Vemana, Pydi Setty, Yelamarthi, Jayaraman, Kandasamy

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