Search Results - Yon, Guk-Hyon

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  1. 1
    Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

    Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes by Yon, Guk-Hyon, Buh, Gyoung Ho, Park, Tai-su, Hong, Soo-Jin, Shin, Yu Gyun, Chung, U-In, Moon, Joo-Tae

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  2. 2
    Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

    Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices by Lee, Jin-Wook, Buh, Gyoung Ho, Yon, Guk-Hyon, Park, Tai-su, Shin, Yu Gyun, Chung, U-In, Moon, Joo-Tae

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  3. 3
    Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

    Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure by Deok-Hyung Lee, Sun-Ghil Lee, Jong Ryeol Yoo, Gyoung-Ho Buh, Guk Hyon Yon, Dong-Woon Shin, Dong Kyu Lee, Hyun-Sook Byun, In Soo Jung, Tai-su Park, Yu Gyun Shin, Siyoung Choi, U-In Chung, Joo-Tae Moon, Byung-Il Ryu

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  4. 4
    Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM

    Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM by Gyoung Ho Buh, Guk-Hyon Yon, Tai-su Park, Jin-Wook Lee, Jihyun Kim, Yun Wang, Lucia Feng, Xiaoru Wang, Yu Gyun Shin, Siyoung Choi, U-In Chung, Joo-Tae Moon, Byung-Il Ryu

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  5. 5
    The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device

    The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device by Jin-Hwa Heo, Soo-Jin Hong, Guk-Hyon Yon, Yu-Gyun Shin, Fujihara, K., U-In Chung, Joo-Tae Moon

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