Search Results - Yue, C.P.

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  1. 1
    Physical modeling of spiral inductors on silicon

    Physical modeling of spiral inductors on silicon by Yue, C.P., Wong, S.S.

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  2. 2
    High-Linearity CMOS T/R Switch Design Above 20 GHz Using Asymmetrical Topology and AC-Floating Bias

    High-Linearity CMOS T/R Switch Design Above 20 GHz Using Asymmetrical Topology and AC-Floating Bias by Piljae Park, Dong Hun Shin, Yue, C.P.

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  3. 3
    Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

    Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications by Talwalkar, N.A., Yue, C.P., Haitao Gan, Wong, S.S.

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  4. 4
    A 10-GHz global clock distribution using coupled standing-wave oscillators

    A 10-GHz global clock distribution using coupled standing-wave oscillators by O'Mahony, F., Yue, C.P., Horowitz, M.A., Wong, S.S.

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  5. 5
    Near speed-of-light signaling over on-chip electrical interconnects

    Near speed-of-light signaling over on-chip electrical interconnects by Chang, R.T., Talwalkar, N., Yue, C.P., Wong, S.S.

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  6. 6
    A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

    A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems by Zargari, M., Su, D.K., Yue, C.P., Rabii, S., Weber, D., Kaczynski, B.J., Mehta, S.S., Singh, K., Mendis, S., Wooley, B.A.

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  7. 7
    Analysis and synthesis of on-chip spiral inductors

    Analysis and synthesis of on-chip spiral inductors by Talwalkar, N.A., Yue, C.P., Wong, S.S.

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  8. 8
    Modeling and optimization of substrate resistance for RF-CMOS

    Modeling and optimization of substrate resistance for RF-CMOS by Chang, R.T., Ming-Ta Yang, Ho, P.P.C., Yo-Jen Wang, Yu-Tai Chia, Boon-Khim Liew, Yue, C.P., Wong, S.S.

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  9. 9
    Kinetics of copper drift in PECVD dielectrics

    Kinetics of copper drift in PECVD dielectrics by Loke, A.L.S., Changsup Ryu, Yue, C.P., Cho, J.S.H., Wong, S.S.

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  10. 10
    On-chip spiral inductors with patterned ground shields for Si-based RF ICs

    On-chip spiral inductors with patterned ground shields for Si-based RF ICs by Yue, C.P., Wong, S.S.

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  11. 11
    Experimental evidence for gyromagnetic damping in magnetic heads determined by impedance measurements up to 9 GHz

    Experimental evidence for gyromagnetic damping in magnetic heads determined by impedance measurements up to 9 GHz by Kaya, A., Yue, C.P., Bain, J.A.

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  12. 12
    An Inductively Coupled Lamb Wave Transducer

    An Inductively Coupled Lamb Wave Transducer by Greve, D.W., Sohn, H., Yue, C.P., Oppenheim, I.J.

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  13. 13
    A 1.2-V, 5.8-mW, Ultra-Wideband Folded Mixer in 0.13-μm CMOS

    A 1.2-V, 5.8-mW, Ultra-Wideband Folded Mixer in 0.13-μm CMOS by Kihwa Choi, Dong Hun Shin, Yue, C.P.

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  14. 14
    A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines

    A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines by Munkyo Seo, Jagannathan, B., Carta, C., Pekarik, J., Chen, L., Yue, C.P., Rodwell, M.

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  15. 15
    A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters

    A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters by Shaeffer, D.K., Shahani, A.R., Mohan, S.S., Samavati, H., Rategh, H.R., del Mar Hershenson, M., Min Xu, Yue, C.P., Eddleman, D.J., Lee, T.H.

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  16. 16
    A unified modeling and design methodology for RFICs using parameterized sub-circuit cells

    A unified modeling and design methodology for RFICs using parameterized sub-circuit cells by Dong Hun Shin, Yue, C.P.

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  17. 17
    WSL: ESD protection for RFIC's: Science or black magic?

    WSL: ESD protection for RFIC's: Science or black magic? by Yue, C.P., Wang, A.

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  18. 18
    A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS

    A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS by Dong Hun Shin, Ji Eun Jang, O'Mahony, F., Yue, C.P.

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  19. 19
    Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz

    Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz by Park, P., Yue, C.P.

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  20. 20
    A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR

    A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR by Jaejin Park, Liu, J.F., Carley, L.R., Yue, C.P.

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