Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function by Zamanlooy, Babak, Mirhassani, Mitra

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Mixed-signal VLSI neural network based on Continuous Valued Number System by Zamanlooy, Babak, Mirhassani, Mitra

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CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning by Zamanlooy, Babak, Mirhassani, Mitra

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Area-efficient robust Madaline based on continuous valued number system by Zamanlooy, Babak, Mirhassani, Mitra

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An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips by Zamanlooy, Babak, Mirhassani, Mitra

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A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS by Pfaff, Dirk, Nummer, Muhammad, Hai, Noman, Xia, Jingjing, Yang, Kai Ge, Mohsenpour, Mohammad-Mahdi, Leong, Choon-Haw C. H., LaCroix, Marc-Andre, Zamanlooy, Babak, Eeckelaert, Tom, Petrov, Dmitry, Haroun, Mostafa, Dick, Carson R., Zaman, Alif, Mei, Haitao, Shakir, Tahseen A., Carvalho, Carlos, Huang, Howard, Kumari, Pratibha, Mason, Ralph, Brishty, Fahmida Pervin, Jaffri, Ifrah, Yokoyama-Martin, David A.

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Review of Arithmetic Operations Using the Continuous Valued Number System by Zamanlooy, Babak, Mirhassani, Mitra, Ahmadi, Majid

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7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS by Pfaff, Dirk, Nummer, Muhammad, Hai, Noman, Xia, Peter, Yang, Kai Ge, Mohsenpour, Mohammad-Mahdi, LaCroix, Marc-Andre, Zamanlooy, Babak, Eeckelaert, Tom, Petrov, Dmitry, Haroun, Mostafa, Dick, Carson, Zaman, Alif, Mei, Haitao, Moazzeni, Shahab, Shakir, Tahseen, Carvalho, Carlos, Huang, Howard, Kumari, Pratibha, Mason, Ralph, Brishty, Fahmida, Jaffri, Ifrah

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A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET by Pfaff, Dirk, Abbott, Robert, Wang, Xin-Jie, Zamanlooy, Babak, Moazzeni, Shahaboddin, Smith, Raleigh, Lin, Chih-Chang

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Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System by Zamanlooy, Babak, Mirhassani, Mitra

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8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2 by LaCroix, Marc-Andre, Chong, Euhan, Shen, Weilun, Nir, Ehud, Musa, Faisal Ahmed, Mei, Haitao, Mohsenpour, Mohammad-Mahdi, Lebedev, Semyon, Zamanlooy, Babak, Carvalho, Carlos, Xin, Qian, Petrov, Dmitry, Wong, Henry, Ho, Huong, Xu, Yang, Shahi, Sina Naderi, Krotnev, Peter, Feist, Chris, Huang, Howard, Tonietto, Davide

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Complexity Study of the Continuous Valued Number System Adders by Zamanlooy, B., Novak, A., Mirhassani, M.

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System-level design of low complexity CVNS feed forward neural network by Mirhassani, M, Zamanlooy, B

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Efficient hardware implementation of threshold neural networks by Zamanlooy, B., Mirhassani, M.

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Modified CAEN-BIST algorithm for better utilization of nanofabrics by Zamanlooy, B., Ayatollahi, A.

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Design of A 100MHz - 1.66GHz, 0.13µm CMOS phase locked loop by Ayat, Mehdi, Babaei, Behnam, Atani, Reza Ebrahimi, Mirzakuchaki, Sattar, Zamanlooy, Babak

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A compact mixer and DAC for implementation of a direct conversion OQPSK transmitter by Chahardori, M., Mehrmanesh, S., Zamanlooy, B., Atarodi, M.

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Design and implementation of a 118 MHz 2D DCT processor by Atani, R.E., Baboli, M., Mirzakuchaki, S., Atani, S.E., Zamanlooy, B.

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Design and implementation of a stable platform digital controller based on DSP by Zamanlooy, B., Takaldani, H.C., Moosavienia, A., Monfaredi, K., Atani, R.E.

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