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A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS
by
Brandolini, Massimo
,
Shin, Young J.
,
Raviprakash, Karthik
,
Tao Wang
,
Rong Wu
,
Geddada, Hemasundar Mohan
,
Yen-Jen Ko
,
Yen Ding
,
Chun-Sheng Huang
,
Wei-Ta Shih
,
Ming-Hung Hsieh
,
Chou, Acer Wei-Te
,
Tianwei Li
,
Shrivastava, Ayaskant
,
Chen, Dominique Yi-Chun
,
Hung, Bryan Juo-Jung
,
Cusmai, Giuseppe
,
Jiangfeng Wu
,
Zhang, Mo Maggie
,
Yuan Yao
,
Unruh, Greg
,
Venes, Ardie
,
Hung Sen Huang
,
Chun-Ying Chen
Published in
IEEE journal of solid-state circuits
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Ieee Journal Of Solid-State Circuits
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Adc
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Calibration
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Clocks
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Direct Sampling
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Engineering
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Engineering, Electrical & Electronic
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Mdac
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Pipeline
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Quantizer
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Receiver
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Receivers
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Sar
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Science & Technology
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Sha-Less
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Signal To Noise Ratio
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Switches
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Technology
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Time Interleaving
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