Search Results - dos Santos, Maico Cassel

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  1. 1
    A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components : (Invited Paper)

    A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components : (Invited Paper) by Dos Santos, Maico Cassel, Jia, Tianyu, Cochet, Martin, Swaminathan, Karthik, Zuckerman, Joseph, Mantovani, Paolo, Giri, Davide, Zhang, Jeff Jun, Loscalzo, Erik Jens, Tombesi, Gabriele, Tien, Kevin, Chandramoorthy, Nandhini, Wellman, John-David, Brooks, David, Wei, Gu-Yeon, Shepard, Kenneth, Carloni, Luca P., Bose, Pradip

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  2. 2
    22.9 A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management

    22.9 A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management by Tambe, Thierry, Zhang, Jeff, Hooper, Coleman, Jia, Tianyu, Whatmough, Paul N., Zuckerman, Joseph, Santos, Maico Cassel Dos, Loscalzo, Erik Jens, Giri, Davide, Shepard, Kenneth, Carloni, Luca, Rush, Alexander, Brooks, David, Wei, Gu-Yeon

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  3. 3
    14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration

    14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration by Dos Santos, Maico Cassel, Jia, Tianyu, Zuckerman, Joseph, Cochet, Martin, Giri, Davide, Loscalzo, Erik Jens, Swaminathan, Karthik, Tambe, Thierry, Zhang, Jeff Jun, Buyuktosunoglu, Alper, Chiu, Kuan-Lin, Guglielmo, Giuseppe Di, Mantovani, Paolo, Piccolboni, Luca, Tombesi, Gabriele, Trilla, David, Wellman, John-David, Yang, En-Yu, Amarnath, Aporva, Jing, Ying, Mishra, Bakshree, Park, Joshua, Suresh, Vignesh, Adve, Sarita, Bose, Pradip, Brooks, David, Carloni, Luca P., Shepard, Kenneth L., Wei, Gu-Yeon

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  4. 4
    A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology

    A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology by Loscalzo, Erik, Cochet, Martin, Zuckerman, Joseph, Zalias, Samira, Lekas, Michael, Cahill, Stephen, Jia, Tianyu, Swaminathan, Karthik, dos Santos, Maico Cassel, Giri, Davide, Sadeghi, Hesam, Meyer, Joseph, Sturcken, Noah, Brooks, David, Wei, Gu-Yeon, Carloni, Luca, Bose, Pradip, Shepard, Kenneth

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  5. 5
    SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs

    SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs by Tombesi, Gabriele, Zuckerman, Joseph, Mantovani, Paolo, Giri, Davide, Santos, Maico Cassel dos, Jia, Tianyu, Brooks, David, Wei, Gu-Yeon, Carloni, Luca P.

    Published in IEEE design and test
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  6. 6
    An adaptive low-power receiver architecture for IEEE 802.15.4 standard

    An adaptive low-power receiver architecture for IEEE 802.15.4 standard by dos Santos, Maico Cassel, Carro, Luigi

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