Yield Improvement by Local Wiring Redundancy

Technology migration from 130 nm to 90 nm has resulted in increased yield loss caused by opens in wiring interconnects and vias. Sensitivity to these defects can be significantly reduced through the use of design methodologies that use arbitrary networks with high degrees of redundancy instead of tr...

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Bibliographic Details
Main Authors: Bickford, Jeanne, Hibbeler, Jason, Buhler, Markus, Koehl, Jurgen, Muller3, Dirk, Peyer, Sven, Schulte, Christian
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Design methodology
Hardware > Electronic design automation > Physical design (EDA)
Hardware > Hardware validation
Hardware > Integrated circuits > Interconnect
Hardware > Integrated circuits > Logic circuits
Joining processes
Mathematics
Microelectronics
Redundancy
Routing
Timing
Wires
Wiring
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Summary:Technology migration from 130 nm to 90 nm has resulted in increased yield loss caused by opens in wiring interconnects and vias. Sensitivity to these defects can be significantly reduced through the use of design methodologies that use arbitrary networks with high degrees of redundancy instead of trees for signal wires. In this paper we describe a technique that improves yield by adding via redundancy through the use of local loops. The commonly used practice of inserting a second via adjacent to an existing via can only be applied to a limited number of vias, generates wrong-way wiring, and does not significantly reduce critical area because of the proximity of the two vias. Industry examples are cited to show that use of local loops to create redundancy reduces critical area, does not require wrong-way wiring, and achieves a higher percent of redundant vias. Addition of local loops does not impact timing or wireability of the design.
ISSN:1948-3287
1948-3295
DOI:10.1109/ISQED.2006.148