Impact of NBTI on SRAM Read Stability and Design for Reliability

• Main Authors: Kumar, Sanjay V., Kim, Chris H., Sapatnekar, Sachin S.
• Format: Conference Proceeding
• Language: English
• Subjects: Cache; Circuit stability; Degradation; Digital circuits; Hardware > Hardware test; Hardware > Hardware validation; Hardware > Integrated circuits > Logic circuits; Hardware > Integrated circuits > Semiconductor memory; Hardware > Integrated circuits > Semiconductor memory > Static memory; Hardware > Robustness; MOS devices; Nanoscale devices; Negative bias temperature instability; Negative Bias Temperature Instability (NBTI); Niobium compounds; Random access memory; Reaction-Diffusion (R-D) Model; SRAM; Static Noise Margin (SNM); Threshold voltage; Titanium compounds
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2006.73

Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.