Interconnect and Thermal-aware Floorplanning for 3D Microprocessors

• Main Authors: Hung, W.-L., Link, G. M., Xie, Yuan, Vijaykrishnan, N., Irwin, M. J.
• Format: Conference Proceeding
• Language: English
• Subjects: Capacitance; Computer architecture; Computer systems organization > Architectures > Parallel architectures > Interconnection architectures; Computer systems organization > Dependable and fault-tolerant systems and networks; Degradation; Energy consumption; General and reference > Cross-computing tools and techniques > Performance; Hardware > Integrated circuits > Interconnect; Integrated circuit interconnections; Integrated circuit technology; Microprocessors; Networks > Network performance evaluation; Repeaters; Temperature; Wires
• ISSN: 1948-3287; 1948-3295
• DOI: 10.1109/ISQED.2006.77

Interconnects are becoming an increasing problem from both performance and power consumption perspective in future technology nodes. The introduction of 3D chip architectures, with their intrinsic capability of reducing wire length, is one of the promising solutions to mitigate the interconnect problem. While interconnect power consumption reduces due to the adoption of 3D designs, the stacking of multiple active layers leads to higher power densities. Thus, high peak temperatures are of major concern in 3D designs. Consequently, we present a thermal-aware floorplanner for 3D architectures. In contrast to most prior work, our floorplanner considers the interconnect power consumption in exploring a thermal-aware floorplan. Our results show that excluding interconnect power can result in peak temperatures being underestimated by as much as 15oC in 90nm technology. Finally, we demonstrate that our floorplanner is effective in lowering peak temperatures using a microprocessor design and four MCNC designs as benchmarks.